Thread (9 messages) read the whole thread 9 messages, 2 authors, 2013-08-19

RE: [PATCH v6 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver

From: Bhushan Bharat-R65777 <hidden>
Date: 2013-08-16 18:24:33
Also in: alsa-devel 

-----Original Message-----
From: Linuxppc-dev [mailto:linuxppc-dev-
bounces+bharat.bhushan=3Dfreescale.com@lists.ozlabs.org] On Behalf Of Nic=
olin Chen
Sent: Friday, August 16, 2013 6:27 PM
To: broonie@kernel.org; lars@metafoo.de; p.zabel@pengutronix.de;
s.hauer@pengutronix.de
Cc: mark.rutland@arm.com; devicetree@vger.kernel.org; alsa-devel@alsa-
project.org; swarren@wwwdotorg.org; festevam@gmail.com; timur@tabi.org;
rob.herring@calxeda.com; tomasz.figa@gmail.com; shawn.guo@linaro.org; lin=
uxppc-
dev@lists.ozlabs.org
Subject: [PATCH v6 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
=20
This patch add S/PDIF controller driver for Freescale SoC.
Please give some more description of the driver?

=20
Signed-off-by: Nicolin Chen <redacted>
---
 .../devicetree/bindings/sound/fsl,spdif.txt        |   56 +
 sound/soc/fsl/Kconfig                              |    3 +
 sound/soc/fsl/Makefile                             |    2 +
 sound/soc/fsl/fsl_spdif.c                          | 1272 ++++++++++++++=
++++++
quoted hunk ↗ jump to hunk
 sound/soc/fsl/fsl_spdif.h                          |  224 ++++
 5 files changed, 1557 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/fsl,spdif.txt
 create mode 100644 sound/soc/fsl/fsl_spdif.c
 create mode 100644 sound/soc/fsl/fsl_spdif.h
=20
diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt
b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
new file mode 100644
index 0000000..5549ce3
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
@@ -0,0 +1,56 @@
+Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
+
+The Freescale S/PDIF audio block is a stereo transceiver that allows the
+processor to receive and transmit digital audio via an coaxial cable or
+a fibre cable.
+
+Required properties:
+
+  - compatible : Compatible list, contains "fsl,<chip>-spdif".
+
+  - reg : Offset and length of the register set for the device.
+
+  - interrupts : Contains spdif interrupt.
+
+  - dmas : Generic dma devicetree binding as described in
+  Documentation/devicetree/bindings/dma/dma.txt.
+
+  - dma-names : Two dmas have to be defined, "tx" and "rx".
+
+  - clocks : Contains an entry for each entry in clock-names.
+
+  - clock-names : Includes the following entries:
+	name		comments
+	"core"		The core clock of spdif controller
+	"rxtx<0-7>"	Clock source list for tx and rx clock.
+			This clock list should be identical to
+			the source list connecting to the spdif
+			clock mux in "SPDIF Transceiver Clock
+			Diagram" of SoC reference manual. It
+			can also be referred to TxClk_Source
+			bit of register SPDIF_STC.
+
+Example:
+
+spdif: spdif@02004000 {
+	compatible =3D "fsl,imx6q-spdif",
+		"fsl,imx35-spdif";
+	reg =3D <0x02004000 0x4000>;
+	interrupts =3D <0 52 0x04>;
+	dmas =3D <&sdma 14 18 0>,
+	       <&sdma 15 18 0>;
+	dma-names =3D "rx", "tx";
+
+	clocks =3D <&clks 197>, <&clks 3>,
+	       <&clks 197>, <&clks 107>,
+	       <&clks 0>, <&clks 118>,
+	       <&clks 62>, <&clks 139>,
+	       <&clks 0>;
+	clock-names =3D "core", "rxtx0",
+		"rxtx1", "rxtx2",
+		"rxtx3", "rxtx4",
+		"rxtx5", "rxtx6",
+		"rxtx7";
+
+	status =3D "okay";
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index e15f771..2c518db 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,6 +1,9 @@
 config SND_SOC_FSL_SSI
 	tristate
=20
+config SND_SOC_FSL_SPDIF
+	tristate
+
 config SND_SOC_FSL_UTILS
 	tristate
=20
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index d4b4aa8..4b5970e 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -12,9 +12,11 @@ obj-$(CONFIG_SND_SOC_P1022_RDK) +=3D snd-soc-p1022-rdk=
.o
quoted hunk ↗ jump to hunk
=20
 # Freescale PowerPC SSI/DMA Platform Support
 snd-soc-fsl-ssi-objs :=3D fsl_ssi.o
+snd-soc-fsl-spdif-objs :=3D fsl_spdif.o
 snd-soc-fsl-utils-objs :=3D fsl_utils.o
 snd-soc-fsl-dma-objs :=3D fsl_dma.o
 obj-$(CONFIG_SND_SOC_FSL_SSI) +=3D snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_FSL_SPDIF) +=3D snd-soc-fsl-spdif.o
 obj-$(CONFIG_SND_SOC_FSL_UTILS) +=3D snd-soc-fsl-utils.o
 obj-$(CONFIG_SND_SOC_POWERPC_DMA) +=3D snd-soc-fsl-dma.o
=20
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
new file mode 100644
index 0000000..e00125e
--- /dev/null
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -0,0 +1,1272 @@
+/*
+ * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Based on stmp3xxx_spdif_dai.c
+ * Vladimir Barinov <vbarinov@embeddedalley.com>
+ * Copyright 2008 SigmaTel, Inc
+ * Copyright 2008 Embedded Alley Solutions, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public Licen=
se
+ * version 2.  This program  is licensed "as is" without any warranty of=
 any
+ * kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/regmap.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+
+#include <sound/asoundef.h>
+#include <sound/soc.h>
+#include <sound/dmaengine_pcm.h>
+
+#include "fsl_spdif.h"
+#include "imx-pcm.h"
+
+#define FSL_SPDIF_TXFIFO_WML	0x8
+#define FSL_SPDIF_RXFIFO_WML	0x8
+
+#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
+#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |
INT_URX_OV|\
+		INT_QRX_FUL | INT_QRX_OV | INT_UQ_SYNC | INT_UQ_ERR |\
+		INT_RXFIFO_RESYNC | INT_LOSS_LOCK | INT_DPLL_LOCKED)
+
+/* Index list for the values that has if (DPLL Locked) condition */
+static u8 srpc_dpll_locked[] =3D { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb, };
										   ^
                                                                     ^ un-n=
ecessary comma.

+#define SRPC_NODPLL_START1	0x5
+#define SRPC_NODPLL_START2	0xc
+
+/*
+ * SPDIF control structure
+ * Defines channel status, subcode and Q sub
+ */
+struct spdif_mixer_control {
+	/* spinlock to access control data */
+	spinlock_t ctl_lock;
+
+	/* IEC958 channel tx status bit */
+	unsigned char ch_status[4];
+
+	/* User bits */
+	unsigned char subcode[2 * SPDIF_UBITS_SIZE];
+
+	/* Q subcode part of user bits */
+	unsigned char qsub[2 * SPDIF_QSUB_SIZE];
+
+	/* buffer ptrs for writer */
+	u32 upos;
+	u32 qpos;
They does not look like pointer?

+
+	/* ready buffer index of the two buffers */
+	u32 ready_buf;
+};
+
+struct fsl_spdif_priv {
+	struct spdif_mixer_control fsl_spdif_control;
+	struct snd_soc_dai_driver cpu_dai_drv;
+	struct platform_device *pdev;
+	struct regmap *regmap;
+	atomic_t dpll_locked;
+	u8 txclk_div[SPDIF_TXRATE_MAX];
+	u8 txclk_src[SPDIF_TXRATE_MAX];
+	u8 rxclk_src;
+	struct clk *txclk[SPDIF_TXRATE_MAX];
+	struct clk *rxclk;
+	struct snd_dmaengine_dai_dma_data dma_params_tx;
+	struct snd_dmaengine_dai_dma_data dma_params_rx;
+
+	/* The name space will be allocated dynamically */
+	char name[0];
+};
+
+
+#ifdef DEBUG
+static void dumpregs(struct fsl_spdif_priv *spdif_priv)
+{
+	struct regmap *regmap =3D spdif_priv->regmap;
+	struct platform_device *pdev =3D spdif_priv->pdev;
+	u32 val, i;
+	int ret;
+
+	/* Valid address set of SPDIF is {[0x0-0x38], 0x44, 0x50} */
+	for (i =3D 0 ; i <=3D REG_SPDIF_STC; i +=3D 4) {
+		ret =3D regmap_read(regmap, REG_SPDIF_SCR + i, &val);
+		if (!ret)
+			dev_dbg(&pdev->dev, "REG 0x%02x =3D 0x%06x\n", i, val);
+	}
+}
+#else
+static void dumpregs(struct fsl_spdif_priv *spdif_priv) {}
+#endif
+
+
+/* DPLL locked and lock loss interrupt handler */
+static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
+{
+	struct regmap *regmap =3D spdif_priv->regmap;
+	struct platform_device *pdev =3D spdif_priv->pdev;
+	u32 locked;
+
+	regmap_read(regmap, REG_SPDIF_SRPC, &locked);
+	locked &=3D SRPC_DPLL_LOCKED;
+
+	dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
+			locked ? "locked" : "loss lock");
+
+	atomic_set(&spdif_priv->dpll_locked, locked ? 1 : 0);
+}
+
+/* Receiver found illegal symbol interrupt handler */
+static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
+{
+	struct regmap *regmap =3D spdif_priv->regmap;
+	struct platform_device *pdev =3D spdif_priv->pdev;
+
+	dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
+
+	if (!atomic_read(&spdif_priv->dpll_locked)) {
+		/* dpll unlocked seems no audio stream */
+		regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
+	}
+}
+
+/* U/Q Channel receive register full */
+static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char =
name)
+{
+	struct spdif_mixer_control *ctrl =3D &spdif_priv->fsl_spdif_control;
+	struct regmap *regmap =3D spdif_priv->regmap;
+	struct platform_device *pdev =3D spdif_priv->pdev;
+	u32 *pos, size, val, reg;
+
+	switch (name) {
+	case 'U':
+		pos =3D &ctrl->upos;
+		size =3D SPDIF_UBITS_SIZE;
+		reg =3D REG_SPDIF_SRU;
+		break;
+	case 'Q':
+		pos =3D &ctrl->qpos;
+		size =3D SPDIF_QSUB_SIZE;
+		reg =3D REG_SPDIF_SRQ;
+		break;
+	default:
+		return;
Should return error.

+	}
+
+	dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
+
+	if (*pos >=3D size * 2) {
+		*pos =3D 0;
+	} else if (unlikely((*pos % size) + 3 > size)) {
+		dev_err(&pdev->dev, "User bit receivce buffer overflow\n");
+		return;
Should return error.

+	}
+
+	regmap_read(regmap, reg, &val);
+	ctrl->subcode[*pos++] =3D val >> 16;
+	ctrl->subcode[*pos++] =3D val >> 8;
+	ctrl->subcode[*pos++] =3D val;
+}
+
+/* U/Q Channel sync found */
+static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
+{
+	struct spdif_mixer_control *ctrl =3D &spdif_priv->fsl_spdif_control;
+	struct platform_device *pdev =3D spdif_priv->pdev;
+
+	dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
+
+	/* U/Q buffer reset */
+	if (ctrl->qpos =3D=3D 0)
+		return;
+
+	/* set ready to this buffer */
+	ctrl->ready_buf =3D (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
+}
+
+/* U/Q Channel framing error */
+static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
+{
+	struct spdif_mixer_control *ctrl =3D &spdif_priv->fsl_spdif_control;
+	struct regmap *regmap =3D spdif_priv->regmap;
+	struct platform_device *pdev =3D spdif_priv->pdev;
+	u32 val;
+
+	dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
+
+	/* read U/Q data and do buffer reset */
+	regmap_read(regmap, REG_SPDIF_SRU, &val);
+	regmap_read(regmap, REG_SPDIF_SRQ, &val);
Above prints says read u/q data and buffer reset, what is buffer reset? Is =
that read on clear?

+
+	/* drop this U/Q buffer */
+	ctrl->ready_buf =3D 0;
+	ctrl->upos =3D 0;
+	ctrl->qpos =3D 0;
+}
+
+/* Get spdif interrupt status and clear the interrupt */
+static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
+{
+	struct regmap *regmap =3D spdif_priv->regmap;
+	u32 val, val2;
+
+	regmap_read(regmap, REG_SPDIF_SIS, &val);
+	regmap_read(regmap, REG_SPDIF_SIE, &val2);
+
+	regmap_write(regmap, REG_SPDIF_SIC, val & val2);
+
+	return val;
+}
+
+static irqreturn_t spdif_isr(int irq, void *devid)
+{
+	struct fsl_spdif_priv *spdif_priv =3D (struct fsl_spdif_priv *)devid;
+	struct platform_device *pdev =3D spdif_priv->pdev;
+	u32 sis;
+
+	sis =3D spdif_intr_status_clear(spdif_priv);
+
+	if (sis & INT_DPLL_LOCKED)
+		spdif_irq_dpll_lock(spdif_priv);
+
+	if (sis & INT_TXFIFO_UNOV)
+		dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
+
+	if (sis & INT_TXFIFO_RESYNC)
+		dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
+
+	if (sis & INT_CNEW)
+		dev_dbg(&pdev->dev, "isr: cstatus new\n");
+
+	if (sis & INT_VAL_NOGOOD)
+		dev_dbg(&pdev->dev, "isr: validity flag no good\n");
+
+	if (sis & INT_SYM_ERR)
+		spdif_irq_sym_error(spdif_priv);
+
+	if (sis & INT_BIT_ERR)
+		dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
+
+	if (sis & INT_URX_FUL)
+		spdif_irq_uqrx_full(spdif_priv, 'U');
+
+	if (sis & INT_URX_OV)
+		dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
+
+	if (sis & INT_QRX_FUL)
+		spdif_irq_uqrx_full(spdif_priv, 'Q');
+
+	if (sis & INT_QRX_OV)
+		dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
+
+	if (sis & INT_UQ_SYNC)
+		spdif_irq_uq_sync(spdif_priv);
+
+	if (sis & INT_UQ_ERR)
+		spdif_irq_uq_err(spdif_priv);
+
+	if (sis & INT_RXFIFO_UNOV)
+		dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
+
+	if (sis & INT_RXFIFO_RESYNC)
+		dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
+
+	if (sis & INT_LOSS_LOCK)
+		spdif_irq_dpll_lock(spdif_priv);
+
+	/* FIXME: Write Tx FIFO to clear TxEm */
+	if (sis & INT_TX_EM)
+		dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
+
+	/* FIXME: Read Rx FIFO to clear RxFIFOFul */
+	if (sis & INT_RXFIFO_FUL)
+		dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
+
+	return IRQ_HANDLED;
+}
+
+static void spdif_softreset(struct fsl_spdif_priv *spdif_priv)
+{
+	struct regmap *regmap =3D spdif_priv->regmap;
+	u32 val, cycle =3D 1000;
+
+	regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
+	regcache_sync(regmap);
+
+	/* RESET bit would be cleared after finishing its reset procedure */
+	do {
+		regmap_read(regmap, REG_SPDIF_SCR, &val);
+	} while ((val & SCR_SOFT_RESET) && cycle--);
What if reset is not cleared and timeout happen?

+}
+
+static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
+				u8 mask, u8 cstatus)
+{
+	ctrl->ch_status[3] &=3D ~mask;
+	ctrl->ch_status[3] |=3D cstatus & mask;
+}
+
+static u8 reverse_bits(u8 input)
+{
+	u8 tmp =3D input;
+
+	tmp =3D ((tmp & 0b10101010) >> 1) | ((tmp << 1) & 0b10101010);
+	tmp =3D ((tmp & 0b11001100) >> 2) | ((tmp << 2) & 0b11001100);
+	tmp =3D ((tmp & 0b11110000) >> 4) | ((tmp << 4) & 0b11110000);
What is this logic, can the hardcoding be removed and some description on a=
bove calculation?


+
+	return tmp;
+}
+
+static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv=
)
+{
+	struct spdif_mixer_control *ctrl =3D &spdif_priv->fsl_spdif_control;
+	struct regmap *regmap =3D spdif_priv->regmap;
+	struct platform_device *pdev =3D spdif_priv->pdev;
+	u32 ch_status;
+
+	ch_status =3D (reverse_bits(ctrl->ch_status[0]) << 16) |
+		(reverse_bits(ctrl->ch_status[1]) << 8) |
+		reverse_bits(ctrl->ch_status[2]);
+	regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
+
+	dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
+
+	ch_status =3D reverse_bits(ctrl->ch_status[3]) << 16;
+	regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
+
+	dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
+}
+
+/* Set SPDIF PhaseConfig register for rx clock */
+static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
+				enum spdif_gainsel gainsel, int dpll_locked)
+{
+	enum spdif_rxclk_src clksrc =3D spdif_priv->rxclk_src;
+	struct regmap *regmap =3D spdif_priv->regmap;
+
+	if (clksrc >=3D SRPC_CLKSRC_MAX || gainsel >=3D GAINSEL_MULTI_MAX)
+		return -EINVAL;
+
+	regmap_update_bits(regmap, REG_SPDIF_SRPC,
+			SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
+			SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
+
+	return 0;
+}
+
+static int spdif_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long rate_actual;
+
+	rate_actual =3D clk_round_rate(clk, rate);
+	clk_set_rate(clk, rate_actual);
+
+	return 0;
+}
+
+static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
+				int sample_rate)
+{
+	struct snd_soc_pcm_runtime *rtd =3D substream->private_data;
+	struct fsl_spdif_priv *spdif_priv =3D snd_soc_dai_get_drvdata(rtd->cpu_=
dai);
+	struct spdif_mixer_control *ctrl =3D &spdif_priv->fsl_spdif_control;
+	struct regmap *regmap =3D spdif_priv->regmap;
+	struct platform_device *pdev =3D spdif_priv->pdev;
+	unsigned long csfs =3D 0;
+	u8 clk =3D -1, div =3D 1;
Not signed type?

+	u32 stc, mask, rate;
+
+	switch (sample_rate) {
+	case 32000:
+		rate =3D SPDIF_TXRATE_32000;
+		csfs =3D IEC958_AES3_CON_FS_32000;
+		break;
+	case 44100:
+		rate =3D SPDIF_TXRATE_44100;
+		csfs =3D IEC958_AES3_CON_FS_44100;
+		break;
+	case 48000:
+		rate =3D SPDIF_TXRATE_48000;
+		csfs =3D IEC958_AES3_CON_FS_48000;
+		break;
+	default:
+		dev_err(&pdev->dev, "unsupported samplerate %d\n", sample_rate);
+		return -EINVAL;
+	}
+
+	clk =3D spdif_priv->txclk_src[rate];
+	div =3D spdif_priv->txclk_div[rate];
+
+	/*
+	 * The S/PDIF block needs a clock of 64 * fs * div.  The S/PDIF block
+	 * will divide by (div).  So request 64 * fs * (div+1) which will
+	 * get rounded.
+	 */
+	spdif_clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (div + 1=
));
+
+	dev_dbg(&pdev->dev, "expected clock rate =3D %d\n",
+			(int)(64 * sample_rate * div));
+	dev_dbg(&pdev->dev, "acutal clock rate =3D %d\n",
+			(int)clk_get_rate(spdif_priv->txclk[rate]));
+
+	/* set fs field in consumer channel status */
+	spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
+
+	/* select clock source and divisor */
+	stc =3D STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | STC_TXCLK_DIV(div);
+	mask =3D STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | STC_TXCLK_DIV_MAS=
K;
+	regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
+
+	dev_dbg(&pdev->dev, "set sample rate to %d\n", sample_rate);
+
+	return 0;
+}
+
+int fsl_spdif_startup(struct snd_pcm_substream *substream,
+			struct snd_soc_dai *cpu_dai)
+{
+	struct snd_soc_pcm_runtime *rtd =3D substream->private_data;
+	struct fsl_spdif_priv *spdif_priv =3D snd_soc_dai_get_drvdata(rtd->cpu_=
dai);
+	struct regmap *regmap =3D spdif_priv->regmap;
+	u32 scr, mask, i;
+
+	/* Reset module and interrupts only for first initialization */
+	if (!cpu_dai->active) {
+		spdif_softreset(spdif_priv);
+
+		/* disable all the interrupts */
+		regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
+	}
+
+	if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) {
+		scr =3D SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
+			SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
+			SCR_TXFIFO_FSEL_IF8;
+		mask =3D SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
+			SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
+			SCR_TXFIFO_FSEL_MASK;
+		for (i =3D 0; i < SPDIF_TXRATE_MAX; i++)
+			clk_enable(spdif_priv->txclk[i]);
+	} else {
+		scr =3D SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
+		mask =3D SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
+			SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
+		clk_enable(spdif_priv->rxclk);
+	}
+	regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
+
+	/* Power up SPDIF module */
+	regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
+
+	return 0;
+}
+
+static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
+				struct snd_soc_dai *cpu_dai)
+{
+	struct snd_soc_pcm_runtime *rtd =3D substream->private_data;
+	struct fsl_spdif_priv *spdif_priv =3D snd_soc_dai_get_drvdata(rtd->cpu_=
dai);
+	struct regmap *regmap =3D spdif_priv->regmap;
+	u32 scr, mask, i;
+
+	if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) {
+		scr =3D 0;
+		mask =3D SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
+			SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
+			SCR_TXFIFO_FSEL_MASK;
+		for (i =3D 0; i < SPDIF_TXRATE_MAX; i++)
+			clk_disable(spdif_priv->txclk[i]);
+	} else {
+		scr =3D SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
+		mask =3D SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
+			SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
+		clk_disable(spdif_priv->rxclk);
+	}
+	regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
+
+	/* Power down SPDIF module only if tx&rx are both inactive */
+	if (!cpu_dai->active) {
+		spdif_intr_status_clear(spdif_priv);
+		regmap_update_bits(regmap, REG_SPDIF_SCR,
+				SCR_LOW_POWER, SCR_LOW_POWER);
+	}
+}
+
+static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params,
+				struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd =3D substream->private_data;
+	struct fsl_spdif_priv *spdif_priv =3D snd_soc_dai_get_drvdata(rtd->cpu_=
dai);
+	struct spdif_mixer_control *ctrl =3D &spdif_priv->fsl_spdif_control;
+	struct platform_device *pdev =3D spdif_priv->pdev;
+	u32 sample_rate =3D params_rate(params);
+	int ret =3D 0;
+
+	if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) {
+		ret  =3D spdif_set_sample_rate(substream, sample_rate);
+		if (ret) {
+			dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
+					__func__, sample_rate);
+			return ret;
+		}
+		spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
+				IEC958_AES3_CON_CLOCK_1000PPM);
+		spdif_write_channel_status(spdif_priv);
+	} else {
+		/* setup rx clock source */
+		ret =3D spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
+	}
+
+	return ret;
+}
+
+static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
+				int cmd, struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd =3D substream->private_data;
+	struct fsl_spdif_priv *spdif_priv =3D snd_soc_dai_get_drvdata(rtd->cpu_=
dai);
+	struct regmap *regmap =3D spdif_priv->regmap;
+	int is_playack =3D (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK)=
;
+	u32 intr =3D is_playack ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE;
+	u32 dmaen =3D is_playack ? SCR_DMA_TX_EN : SCR_DMA_RX_EN;;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
+		regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
+		dumpregs(spdif_priv);
+		break;
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
+		regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+struct snd_soc_dai_ops fsl_spdif_dai_ops =3D {
+	.startup =3D fsl_spdif_startup,
+	.hw_params =3D fsl_spdif_hw_params,
+	.trigger =3D fsl_spdif_trigger,
+	.shutdown =3D fsl_spdif_shutdown,
+};
+
+
+/*
+ * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+ * FSL SPDIF IEC958 controller(mixer) functions
+ *
+ *	Channel status get/put control
+ *	User bit value get/put control
+ *	Valid bit value get control
+ *	DPLL lock status get control
+ *	User bit sync mode selection control
+ * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+ */
+
+static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type =3D SNDRV_CTL_ELEM_TYPE_IEC958;
+	uinfo->count =3D 1;
+
+	return 0;
+}
+
+static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *uvalue)
+{
+	struct snd_soc_dai *cpu_dai =3D snd_kcontrol_chip(kcontrol);
+	struct fsl_spdif_priv *spdif_priv =3D snd_soc_dai_get_drvdata(cpu_dai);
+	struct spdif_mixer_control *ctrl =3D &spdif_priv->fsl_spdif_control;
+
+	uvalue->value.iec958.status[0] =3D ctrl->ch_status[0];
+	uvalue->value.iec958.status[1] =3D ctrl->ch_status[1];
+	uvalue->value.iec958.status[2] =3D ctrl->ch_status[2];
+	uvalue->value.iec958.status[3] =3D ctrl->ch_status[3];
+
+	return 0;
+}
+
+static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *uvalue)
+{
+	struct snd_soc_dai *cpu_dai =3D snd_kcontrol_chip(kcontrol);
+	struct fsl_spdif_priv *spdif_priv =3D snd_soc_dai_get_drvdata(cpu_dai);
+	struct spdif_mixer_control *ctrl =3D &spdif_priv->fsl_spdif_control;
+
+	ctrl->ch_status[0] =3D uvalue->value.iec958.status[0];
+	ctrl->ch_status[1] =3D uvalue->value.iec958.status[1];
+	ctrl->ch_status[2] =3D uvalue->value.iec958.status[2];
+	ctrl->ch_status[3] =3D uvalue->value.iec958.status[3];
+
+	spdif_write_channel_status(spdif_priv);
+
+	return 0;
+}
+
+/* Get channel status from SPDIF_RX_CCHAN register */
+static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_dai *cpu_dai =3D snd_kcontrol_chip(kcontrol);
+	struct fsl_spdif_priv *spdif_priv =3D snd_soc_dai_get_drvdata(cpu_dai);
+	struct regmap *regmap =3D spdif_priv->regmap;
+	u32 cstatus, val;
+
+	regmap_read(regmap, REG_SPDIF_SIS, &val);
+	if (!(val & INT_CNEW)) {
+		return -EAGAIN;
+	}
+
+	regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
+	ucontrol->value.iec958.status[0] =3D (cstatus >> 16) & 0xFF;
+	ucontrol->value.iec958.status[1] =3D (cstatus >> 8) & 0xFF;
+	ucontrol->value.iec958.status[2] =3D cstatus & 0xFF;
+
+	regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
+	ucontrol->value.iec958.status[3] =3D (cstatus >> 16) & 0xFF;
+	ucontrol->value.iec958.status[4] =3D (cstatus >> 8) & 0xFF;
+	ucontrol->value.iec958.status[5] =3D cstatus & 0xFF;
+
+	/* clear intr */
+	regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
+
+	return 0;
+}
+
+/*
+ * Get User bits (subcode) from chip value which readed out
+ * in UChannel register.
+ */
+static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_dai *cpu_dai =3D snd_kcontrol_chip(kcontrol);
+	struct fsl_spdif_priv *spdif_priv =3D snd_soc_dai_get_drvdata(cpu_dai);
+	struct spdif_mixer_control *ctrl =3D &spdif_priv->fsl_spdif_control;
+	unsigned long flags;
+	int ret =3D 0;
+
+	spin_lock_irqsave(&ctrl->ctl_lock, flags);
+	if (ctrl->ready_buf) {
+		int idx =3D (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
+		memcpy(&ucontrol->value.iec958.subcode[0],
+				&ctrl->subcode[idx], SPDIF_UBITS_SIZE);
+	} else {
+		ret =3D -EAGAIN;
+	}
+	spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
+
+	return ret;
+}
+
+/* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */
+static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type =3D SNDRV_CTL_ELEM_TYPE_BYTES;
+	uinfo->count =3D SPDIF_QSUB_SIZE;
+
+	return 0;
+}
+
+/* Get Q subcode from chip value which readed out in QChannel register *=
/
+static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_dai *cpu_dai =3D snd_kcontrol_chip(kcontrol);
+	struct fsl_spdif_priv *spdif_priv =3D snd_soc_dai_get_drvdata(cpu_dai);
+	struct spdif_mixer_control *ctrl =3D &spdif_priv->fsl_spdif_control;
+	unsigned long flags;
+	int ret =3D 0;
+
+	spin_lock_irqsave(&ctrl->ctl_lock, flags);
+	if (ctrl->ready_buf) {
+		int idx =3D (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
+		memcpy(&ucontrol->value.bytes.data[0],
+				&ctrl->qsub[idx], SPDIF_QSUB_SIZE);
+	} else {
+		ret =3D -EAGAIN;
+	}
+	spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
+
+	return ret;
+}
+
+/* Valid bit infomation */
+static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type =3D SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+	uinfo->count =3D 1;
+	uinfo->value.integer.min =3D 0;
+	uinfo->value.integer.max =3D 1;
+
+	return 0;
+}
+
+/* Get valid good bit from interrupt status register */
+static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_dai *cpu_dai =3D snd_kcontrol_chip(kcontrol);
+	struct fsl_spdif_priv *spdif_priv =3D snd_soc_dai_get_drvdata(cpu_dai);
+	struct regmap *regmap =3D spdif_priv->regmap;
+	u32 val;
+
+	val =3D regmap_read(regmap, REG_SPDIF_SIS, &val);
+	ucontrol->value.integer.value[0] =3D (val & INT_VAL_NOGOOD) !=3D 0;
+	regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
+
+	return 0;
+}
+
+/* DPLL lock infomation */
+static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type =3D SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count =3D 1;
+	uinfo->value.integer.min =3D 16000;
+	uinfo->value.integer.max =3D 96000;
+
+	return 0;
+}
+
+static u32 gainsel_multi[GAINSEL_MULTI_MAX] =3D {
+	24, 16, 12, 8, 6, 4, 3,
+};
+
+/* Get RX data clock rate given the SPDIF bus_clk */
+static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
+				enum spdif_gainsel gainsel)
+{
+	struct regmap *regmap =3D spdif_priv->regmap;
+	struct platform_device *pdev =3D spdif_priv->pdev;
+	u64 tmpval64, busclk_freq =3D 0;
+	u32 freqmeas, phaseconf;
+	enum spdif_rxclk_src clksrc;
+
+	regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
+	regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
+
+	clksrc =3D (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
+	if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) {
+		/* get bus clock from system */
+		busclk_freq =3D clk_get_rate(spdif_priv->rxclk);
+	}
+
+	/* FreqMeas_CLK =3D (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
+	tmpval64 =3D (u64) busclk_freq * freqmeas;
+	do_div(tmpval64, gainsel_multi[gainsel] * 1024);
+	do_div(tmpval64, 128 * 1024);
+
+	dev_dbg(&pdev->dev, "FreqMeas: %d\n", (int)freqmeas);
+	dev_dbg(&pdev->dev, "BusclkFreq: %d\n", (int)busclk_freq);
+	dev_dbg(&pdev->dev, "RxRate: %d\n", (int)tmpval64);
+
+	return (int)tmpval64;
+}
+
+/*
+ * Get DPLL lock or not info from stable interrupt status register.
+ * User application must use this control to get locked,
+ * then can do next PCM operation
+ */
+static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_dai *cpu_dai =3D snd_kcontrol_chip(kcontrol);
+	struct fsl_spdif_priv *spdif_priv =3D snd_soc_dai_get_drvdata(cpu_dai);
+	int rate =3D spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
+
+	if (atomic_read(&spdif_priv->dpll_locked))
+		ucontrol->value.integer.value[0] =3D rate;
+	else
+		ucontrol->value.integer.value[0] =3D 0;
+
+	return 0;
+}
+
+/* User bit sync mode info */
+static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type =3D SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+	uinfo->count =3D 1;
+	uinfo->value.integer.min =3D 0;
+	uinfo->value.integer.max =3D 1;
+
+	return 0;
+}
+
+/*
+ * User bit sync mode:
+ * 1 CD User channel subcode
+ * 0 Non-CD data
+ */
+static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
+			       struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_dai *cpu_dai =3D snd_kcontrol_chip(kcontrol);
+	struct fsl_spdif_priv *spdif_priv =3D snd_soc_dai_get_drvdata(cpu_dai);
+	struct regmap *regmap =3D spdif_priv->regmap;
+	u32 val;
+
+	regmap_read(regmap, REG_SPDIF_SRCD, &val);
+	ucontrol->value.integer.value[0] =3D (val & SRCD_CD_USER) !=3D 0;
+
+	return 0;
+}
+
+/*
+ * User bit sync mode:
+ * 1 CD User channel subcode
+ * 0 Non-CD data
+ */
+static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_dai *cpu_dai =3D snd_kcontrol_chip(kcontrol);
+	struct fsl_spdif_priv *spdif_priv =3D snd_soc_dai_get_drvdata(cpu_dai);
+	struct regmap *regmap =3D spdif_priv->regmap;
+	u32 val =3D ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
+
+	regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
+
+	return 0;
+}
+
+/* FSL SPDIF IEC958 controller defines */
+static struct snd_kcontrol_new fsl_spdif_ctrls[] =3D {
+	/* status cchanel controller */
+	{
+		.iface =3D SNDRV_CTL_ELEM_IFACE_MIXER,
+		.name =3D SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
+		.access =3D SNDRV_CTL_ELEM_ACCESS_READ |
+			SNDRV_CTL_ELEM_ACCESS_WRITE |
+			SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+		.info =3D fsl_spdif_info,
+		.get =3D fsl_spdif_pb_get,
+		.put =3D fsl_spdif_pb_put,
+	},
+	{
+		.iface =3D SNDRV_CTL_ELEM_IFACE_PCM,
+		.name =3D SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
+		.access =3D SNDRV_CTL_ELEM_ACCESS_READ |
+			SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+		.info =3D fsl_spdif_info,
+		.get =3D fsl_spdif_capture_get,
+	},
+	/* user bits controller */
+	{
+		.iface =3D SNDRV_CTL_ELEM_IFACE_PCM,
+		.name =3D "IEC958 Subcode Capture Default",
+		.access =3D SNDRV_CTL_ELEM_ACCESS_READ |
+			SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+		.info =3D fsl_spdif_info,
+		.get =3D fsl_spdif_subcode_get,
+	},
+	{
+		.iface =3D SNDRV_CTL_ELEM_IFACE_PCM,
+		.name =3D "IEC958 Q-subcode Capture Default",
+		.access =3D SNDRV_CTL_ELEM_ACCESS_READ |
+			SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+		.info =3D fsl_spdif_qinfo,
+		.get =3D fsl_spdif_qget,
+	},
+	/* valid bit error controller */
+	{
+		.iface =3D SNDRV_CTL_ELEM_IFACE_PCM,
+		.name =3D "IEC958 V-Bit Errors",
+		.access =3D SNDRV_CTL_ELEM_ACCESS_READ |
+			SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+		.info =3D fsl_spdif_vbit_info,
+		.get =3D fsl_spdif_vbit_get,
+	},
+	/* DPLL lock info get controller */
+	{
+		.iface =3D SNDRV_CTL_ELEM_IFACE_PCM,
+		.name =3D "RX Sample Rate",
+		.access =3D SNDRV_CTL_ELEM_ACCESS_READ |
+			SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+		.info =3D fsl_spdif_rxrate_info,
+		.get =3D fsl_spdif_rxrate_get,
+	},
+	/* User bit sync mode set/get controller */
+	{
+		.iface =3D SNDRV_CTL_ELEM_IFACE_PCM,
+		.name =3D "IEC958 USyncMode CDText",
+		.access =3D SNDRV_CTL_ELEM_ACCESS_READ |
+			SNDRV_CTL_ELEM_ACCESS_WRITE |
+			SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+		.info =3D fsl_spdif_usync_info,
+		.get =3D fsl_spdif_usync_get,
+		.put =3D fsl_spdif_usync_put,
+	},
+};
+
+static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
+{
+	struct fsl_spdif_priv *spdif_private =3D snd_soc_dai_get_drvdata(dai);
+
+	dai->playback_dma_data =3D &spdif_private->dma_params_tx;
+	dai->capture_dma_data =3D &spdif_private->dma_params_rx;
+
+	snd_soc_add_dai_controls(dai, fsl_spdif_ctrls,
ARRAY_SIZE(fsl_spdif_ctrls));
+
+	return 0;
+}
+
+struct snd_soc_dai_driver fsl_spdif_dai =3D {
+	.probe =3D &fsl_spdif_dai_probe,
+	.playback =3D {
+		.channels_min =3D 2,
+		.channels_max =3D 2,
+		.rates =3D FSL_SPDIF_RATES_PLAYBACK,
+		.formats =3D FSL_SPDIF_FORMATS_PLAYBACK,
+	},
+	.capture =3D {
+		.channels_min =3D 2,
+		.channels_max =3D 2,
+		.rates =3D FSL_SPDIF_RATES_CAPTURE,
+		.formats =3D FSL_SPDIF_FORMATS_CAPTURE,
+	},
+	.ops =3D &fsl_spdif_dai_ops,
+};
+
+static const struct snd_soc_component_driver fsl_spdif_component =3D {
+	.name		=3D "fsl-spdif",
+};
+
+/*
+ * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+ * FSL SPDIF REGMAP
+ * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+ */
+
+static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case REG_SPDIF_SCR:
+	case REG_SPDIF_SRCD:
+	case REG_SPDIF_SRPC:
+	case REG_SPDIF_SIE:
+	case REG_SPDIF_SIS:
+	case REG_SPDIF_SRL:
+	case REG_SPDIF_SRR:
+	case REG_SPDIF_SRCSH:
+	case REG_SPDIF_SRCSL:
+	case REG_SPDIF_SRU:
+	case REG_SPDIF_SRQ:
+	case REG_SPDIF_STCSCH:
+	case REG_SPDIF_STCSCL:
+	case REG_SPDIF_SRFM:
+	case REG_SPDIF_STC:
+		return true;
+	default:
+		return false;
+	};
+}
+
+static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg=
)
+{
+	switch (reg) {
+	case REG_SPDIF_SCR:
+	case REG_SPDIF_SRCD:
+	case REG_SPDIF_SRPC:
+	case REG_SPDIF_SIE:
+	case REG_SPDIF_SIC:
+	case REG_SPDIF_STL:
+	case REG_SPDIF_STR:
+	case REG_SPDIF_STCSCH:
+	case REG_SPDIF_STCSCL:
+	case REG_SPDIF_STC:
+		return true;
+	default:
+		return false;
+	};
+}
+
+static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
+{
+	/* Sync all registers after reset */
Where us sync :) ?

-Bharat

+	return true;
+}
+
+static const struct regmap_config fsl_spdif_regmap_config =3D {
+	.reg_bits =3D 32,
+	.reg_stride =3D 4,
+	.val_bits =3D 32,
+
+	.max_register =3D REG_SPDIF_STC,
+	.readable_reg =3D fsl_spdif_readable_reg,
+	.writeable_reg =3D fsl_spdif_writeable_reg,
+	.volatile_reg =3D fsl_spdif_volatile_reg,
+	.cache_type =3D REGCACHE_RBTREE,
+};
+
+static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
+				struct clk *clk, u64 savesub,
+				enum spdif_txrate index)
+{
+	const u32 rate[] =3D { 32000, 44100, 48000, };
+	u64 rate_ideal, rate_actual, sub;
+	u32 div, arate;
+
+	for (div =3D 1; div <=3D 128; div++) {
+		rate_ideal =3D rate[index] * (div + 1) * 64;
+		rate_actual =3D clk_round_rate(clk, rate_ideal);
+
+		arate =3D rate_actual / 64;
+		arate /=3D div;
+
+		if (arate =3D=3D rate[index]) {
+			/* We are lucky */
+			savesub =3D 0;
+			spdif_priv->txclk_div[index] =3D div;
+			break;
+		} else if (arate / rate[index] =3D=3D 1) {
+			/* A little bigger than expect */
+			sub =3D (arate - rate[index]) * 100000;
+			do_div(sub, rate[index]);
+			if (sub < savesub) {
+				savesub =3D sub;
+				spdif_priv->txclk_div[index] =3D div;
+			}
+		} else if (rate[index] / arate =3D=3D 1) {
+			/* A little smaller than expect */
+			sub =3D (rate[index] - arate) * 100000;
+			do_div(sub, rate[index]);
+			if (sub < savesub) {
+				savesub =3D sub;
+				spdif_priv->txclk_div[index] =3D div;
+			}
+		}
+	}
+
+	return savesub;
+}
+
+static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
+				enum spdif_txrate index)
+{
+	const u32 rate[] =3D { 32000, 44100, 48000, };
+	struct platform_device *pdev =3D spdif_priv->pdev;
+	struct device *dev =3D &pdev->dev;
+	u64 savesub =3D 100000, ret;
+	struct clk *clk;
+	char tmp[16];
+	int i;
+
+	for (i =3D 0; i < STC_TXCLK_SRC_MAX; i++) {
+		sprintf(tmp, "rxtx%d", i);
+		clk =3D devm_clk_get(&pdev->dev, tmp);
+		if (IS_ERR(clk)) {
+			dev_err(dev, "no rxtx%d property in devicetree\n", i);
+			return PTR_ERR(clk);
+		}
+		if (!clk_get_rate(clk))
+			continue;
+
+		ret =3D fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index);
+		if (savesub =3D=3D ret)
+			continue;
+
+		savesub =3D ret;
+		spdif_priv->txclk[index] =3D clk;
+		spdif_priv->txclk_src[index] =3D i;
+
+		/* To quick catch a divisor, we allow a 0.1% deviation */
+		if (savesub < 100)
+			break;
+	}
+
+	dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate=
",
+			spdif_priv->txclk_src[index], rate[index]);
+	dev_dbg(&pdev->dev, "use divisor %d for %dHz sample rate",
+			spdif_priv->txclk_div[index], rate[index]);
+
+	return 0;
+}
+
+static int fsl_spdif_probe(struct platform_device *pdev)
+{
+	struct device_node *np =3D pdev->dev.of_node;
+	struct fsl_spdif_priv *spdif_priv;
+	struct spdif_mixer_control *ctrl;
+	struct resource *res;
+	void __iomem *regs;
+	int irq, ret, i;
+
+	if (!np)
+		return -ENODEV;
+
+	spdif_priv =3D devm_kzalloc(&pdev->dev,
+			sizeof(struct fsl_spdif_priv) + strlen(np->name) + 1,
GFP_KERNEL);
+	if (!spdif_priv) {
+		dev_err(&pdev->dev, "could not allocate DAI object\n");
+		return -ENOMEM;
+	}
+
+	strcpy(spdif_priv->name, np->name);
+
+	spdif_priv->pdev =3D pdev;
+
+	/* Initialize this copy of the CPU DAI driver structure */
+	memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai))=
;
quoted hunk ↗ jump to hunk
+	spdif_priv->cpu_dai_drv.name =3D spdif_priv->name;
+
+	/* Get the addresses and IRQ */
+	res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (IS_ERR(res)) {
+		dev_err(&pdev->dev, "could not determine device resources\n");
+		return PTR_ERR(res);
+	}
+
+	regs =3D devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(regs)) {
+		dev_err(&pdev->dev, "could not map device resources\n");
+		return PTR_ERR(regs);
+	}
+
+	spdif_priv->regmap =3D devm_regmap_init_mmio_clk(&pdev->dev,
+			"core", regs, &fsl_spdif_regmap_config);
+	if (IS_ERR(spdif_priv->regmap)) {
+		dev_err(&pdev->dev, "regmap init failed\n");
+		return PTR_ERR(spdif_priv->regmap);
+	}
+
+	irq =3D platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
+		return irq;
+	}
+
+	ret =3D devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
+			spdif_priv->name, spdif_priv);
+	if (ret) {
+		dev_err(&pdev->dev, "could not claim irq %u\n", irq);
+		return ret;
+	}
+
+	/* Select clock source for rx/tx clock */
+	spdif_priv->rxclk =3D devm_clk_get(&pdev->dev, "rxtx1");
+	if (IS_ERR(spdif_priv->rxclk)) {
+		dev_err(&pdev->dev, "no rxtx1 property in devicetree\n");
+		return PTR_ERR(spdif_priv->rxclk);
+	}
+	spdif_priv->rxclk_src =3D DEFAULT_RXCLK_SRC;
+
+	for (i =3D 0; i < SPDIF_TXRATE_MAX; i++) {
+		ret =3D fsl_spdif_probe_txclk(spdif_priv, i);
+		if (ret)
+			return ret;
+	}
+
+	/* Prepare rx/tx clock */
+	clk_prepare(spdif_priv->rxclk);
+	for (i =3D 0; i < SPDIF_TXRATE_MAX; i++)
+		clk_prepare(spdif_priv->txclk[i]);
+
+	/* initial spinlock for control data */
+	ctrl =3D &spdif_priv->fsl_spdif_control;
+	spin_lock_init(&ctrl->ctl_lock);
+
+	/* init tx channel status default value */
+	ctrl->ch_status[0] =3D
+		IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_5015;
+	ctrl->ch_status[1] =3D IEC958_AES1_CON_DIGDIGCONV_ID;
+	ctrl->ch_status[2] =3D 0x00;
+	ctrl->ch_status[3] =3D
+		IEC958_AES3_CON_FS_44100 | IEC958_AES3_CON_CLOCK_1000PPM;
+
+	atomic_set(&spdif_priv->dpll_locked, 0);
+
+	spdif_priv->dma_params_tx.maxburst =3D FSL_SPDIF_TXFIFO_WML;
+	spdif_priv->dma_params_rx.maxburst =3D FSL_SPDIF_RXFIFO_WML;
+	spdif_priv->dma_params_tx.addr =3D res->start + REG_SPDIF_STL;
+	spdif_priv->dma_params_rx.addr =3D res->start + REG_SPDIF_SRL;
+
+	/* Register with ASoC */
+	dev_set_drvdata(&pdev->dev, spdif_priv);
+
+	ret =3D snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
+					 &spdif_priv->cpu_dai_drv, 1);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
+		goto error_dev;
+	}
+
+	ret =3D imx_pcm_dma_init(pdev);
+	if (ret) {
+		dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
+		goto error_component;
+	}
+
+	return ret;
+
+error_component:
+	snd_soc_unregister_component(&pdev->dev);
+error_dev:
+	dev_set_drvdata(&pdev->dev, NULL);
+	for (i =3D 0; i < SPDIF_TXRATE_MAX; i++)
+		clk_unprepare(spdif_priv->txclk[i]);
+	clk_unprepare(spdif_priv->rxclk);
+
+	return ret;
+}
+
+static int fsl_spdif_remove(struct platform_device *pdev)
+{
+	struct fsl_spdif_priv *spdif_priv =3D platform_get_drvdata(pdev);
+	int i;
+
+	imx_pcm_dma_exit(pdev);
+	snd_soc_unregister_component(&pdev->dev);
+
+	for (i =3D 0; i < SPDIF_TXRATE_MAX; i++)
+		clk_unprepare(spdif_priv->txclk[i]);
+	clk_unprepare(spdif_priv->rxclk);
+
+	dev_set_drvdata(&pdev->dev, NULL);
+
+	return 0;
+}
+
+static const struct of_device_id fsl_spdif_dt_ids[] =3D {
+	{ .compatible =3D "fsl,imx35-spdif", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
+
+static struct platform_driver fsl_spdif_driver =3D {
+	.driver =3D {
+		.name =3D "fsl-spdif-dai",
+		.owner =3D THIS_MODULE,
+		.of_match_table =3D fsl_spdif_dt_ids,
+	},
+	.probe =3D fsl_spdif_probe,
+	.remove =3D fsl_spdif_remove,
+};
+
+module_platform_driver(fsl_spdif_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:fsl-spdif-dai");
diff --git a/sound/soc/fsl/fsl_spdif.h b/sound/soc/fsl/fsl_spdif.h
new file mode 100644
index 0000000..f8357f6
--- /dev/null
+++ b/sound/soc/fsl/fsl_spdif.h
@@ -0,0 +1,224 @@
+/*
+ * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Nicolin Chen <b42378@freescale.com>
+ *
+ * Based on fsl_ssi.h
+ * Author: Timur Tabi <timur@freescale.com>
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public Licen=
se
+ * version 2.  This program  is licensed "as is" without any warranty of=
 any
+ * kind, whether express or implied.
+ */
+
+#ifndef _FSL_SPDIF_DAI_H
+#define _FSL_SPDIF_DAI_H
+
+/* S/PDIF Register Map */
+#define REG_SPDIF_SCR 			0x0	/* SPDIF Configuration Register */
+#define REG_SPDIF_SRCD		 	0x4	/* CDText Control Register */
+#define REG_SPDIF_SRPC			0x8	/* PhaseConfig Register */
+#define REG_SPDIF_SIE			0xc	/* InterruptEn Register */
+#define REG_SPDIF_SIS			0x10	/* InterruptStat Register */
+#define REG_SPDIF_SIC			0x10	/* InterruptClear Register */
+#define REG_SPDIF_SRL			0x14	/* SPDIFRxLeft Register */
+#define REG_SPDIF_SRR			0x18	/* SPDIFRxRight Register */
+#define REG_SPDIF_SRCSH			0x1c	/* SPDIFRxCChannel_h Register */
+#define REG_SPDIF_SRCSL			0x20	/* SPDIFRxCChannel_l Register */
+#define REG_SPDIF_SRU			0x24	/* UchannelRx Register */
+#define REG_SPDIF_SRQ			0x28	/* QchannelRx Register */
+#define REG_SPDIF_STL			0x2C	/* SPDIFTxLeft Register */
+#define REG_SPDIF_STR			0x30	/* SPDIFTxRight Register */
+#define REG_SPDIF_STCSCH		0x34	/* SPDIFTxCChannelCons_h Register */
+#define REG_SPDIF_STCSCL		0x38	/* SPDIFTxCChannelCons_l Register */
+#define REG_SPDIF_SRFM			0x44	/* FreqMeas Register */
+#define REG_SPDIF_STC			0x50	/* SPDIFTxClk Register */
+
+
+/* SPDIF Configuration register */
+#define SCR_RXFIFO_CTL_OFFSET		23
+#define SCR_RXFIFO_CTL_MASK		(1 << SCR_RXFIFO_CTL_OFFSET)
+#define SCR_RXFIFO_CTL_ZERO		(1 << SCR_RXFIFO_CTL_OFFSET)
+#define SCR_RXFIFO_OFF_OFFSET		22
+#define SCR_RXFIFO_OFF_MASK		(1 << SCR_RXFIFO_OFF_OFFSET)
+#define SCR_RXFIFO_OFF			(1 << SCR_RXFIFO_OFF_OFFSET)
+#define SCR_RXFIFO_RST_OFFSET		21
+#define SCR_RXFIFO_RST_MASK		(1 << SCR_RXFIFO_RST_OFFSET)
+#define SCR_RXFIFO_RST			(1 << SCR_RXFIFO_RST_OFFSET)
+#define SCR_RXFIFO_FSEL_OFFSET		19
+#define SCR_RXFIFO_FSEL_MASK		(0x3 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF0		(0x0 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF4		(0x1 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF8		(0x2 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF12		(0x3 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_AUTOSYNC_OFFSET	18
+#define SCR_RXFIFO_AUTOSYNC_MASK	(1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
+#define SCR_RXFIFO_AUTOSYNC		(1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_AUTOSYNC_OFFSET	17
+#define SCR_TXFIFO_AUTOSYNC_MASK	(1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_AUTOSYNC		(1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_FSEL_OFFSET		15
+#define SCR_TXFIFO_FSEL_MASK		(0x3 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF0		(0x0 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF4		(0x1 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF8		(0x2 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF12		(0x3 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_LOW_POWER			(1 << 13)
+#define SCR_SOFT_RESET			(1 << 12)
+#define SCR_TXFIFO_CTRL_OFFSET		10
+#define SCR_TXFIFO_CTRL_MASK		(0x3 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_ZERO		(0x0 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_NORMAL		(0x1 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_ONESAMPLE	(0x2 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_DMA_RX_EN_OFFSET		9
+#define SCR_DMA_RX_EN_MASK		(1 << SCR_DMA_RX_EN_OFFSET)
+#define SCR_DMA_RX_EN			(1 << SCR_DMA_RX_EN_OFFSET)
+#define SCR_DMA_TX_EN_OFFSET		8
+#define SCR_DMA_TX_EN_MASK		(1 << SCR_DMA_TX_EN_OFFSET)
+#define SCR_DMA_TX_EN			(1 << SCR_DMA_TX_EN_OFFSET)
+#define SCR_VAL_OFFSET			5
+#define SCR_VAL_MASK			(1 << SCR_VAL_OFFSET)
+#define SCR_VAL_CLEAR			(1 << SCR_VAL_OFFSET)
+#define SCR_TXSEL_OFFSET		2
+#define SCR_TXSEL_MASK			(0x7 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_OFF			(0 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_RX			(1 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_NORMAL		(0x5 << SCR_TXSEL_OFFSET)
+#define SCR_USRC_SEL_OFFSET		0x0
+#define SCR_USRC_SEL_MASK		(0x3 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_NONE		(0x0 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_RECV		(0x1 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_CHIP		(0x3 << SCR_USRC_SEL_OFFSET)
+
+/* SPDIF CDText control */
+#define SRCD_CD_USER_OFFSET		1
+#define SRCD_CD_USER			(1 << SRCD_CD_USER_OFFSET)
+
+/* SPDIF Phase Configuration register */
+#define SRPC_DPLL_LOCKED		(1 << 6)
+#define SRPC_CLKSRC_SEL_OFFSET		7
+#define SRPC_CLKSRC_SEL_MASK		(0xf << SRPC_CLKSRC_SEL_OFFSET)
+#define SRPC_CLKSRC_SEL_SET(x)		((x << SRPC_CLKSRC_SEL_OFFSET) &
SRPC_CLKSRC_SEL_MASK)
+#define SRPC_CLKSRC_SEL_LOCKED_OFFSET1	5
+#define SRPC_CLKSRC_SEL_LOCKED_OFFSET2	2
+#define SRPC_GAINSEL_OFFSET		3
+#define SRPC_GAINSEL_MASK		(0x7 << SRPC_GAINSEL_OFFSET)
+#define SRPC_GAINSEL_SET(x)		((x << SRPC_GAINSEL_OFFSET) &
SRPC_GAINSEL_MASK)
+
+/* SPDIF rx clock source */
+enum spdif_rxclk_src {
+	SRPC_CLKSRC_0 =3D 0,
+	SRPC_CLKSRC_1,
+	SRPC_CLKSRC_2,
+	SRPC_CLKSRC_3,
+	SRPC_CLKSRC_4,
+	SRPC_CLKSRC_5,
+	SRPC_CLKSRC_6,
+	SRPC_CLKSRC_7,
+	SRPC_CLKSRC_8,
+	SRPC_CLKSRC_9,
+	SRPC_CLKSRC_10,
+	SRPC_CLKSRC_11,
+	SRPC_CLKSRC_12,
+	SRPC_CLKSRC_13,
+	SRPC_CLKSRC_14,
+	SRPC_CLKSRC_15,
+};
+#define SRPC_CLKSRC_MAX			(SRPC_CLKSRC_15 + 1)
+#define DEFAULT_RXCLK_SRC		SRPC_CLKSRC_1
+
+enum spdif_gainsel {
+	GAINSEL_MULTI_24 =3D 0,
+	GAINSEL_MULTI_16,
+	GAINSEL_MULTI_12,
+	GAINSEL_MULTI_8,
+	GAINSEL_MULTI_6,
+	GAINSEL_MULTI_4,
+	GAINSEL_MULTI_3,
+};
+#define GAINSEL_MULTI_MAX		(GAINSEL_MULTI_3 + 1)
+#define SPDIF_DEFAULT_GAINSEL		GAINSEL_MULTI_8
+
+/* SPDIF interrupt mask define */
+#define INT_DPLL_LOCKED			(1 << 20)
+#define INT_TXFIFO_UNOV			(1 << 19)
+#define INT_TXFIFO_RESYNC		(1 << 18)
+#define INT_CNEW			(1 << 17)
+#define INT_VAL_NOGOOD			(1 << 16)
+#define INT_SYM_ERR			(1 << 15)
+#define INT_BIT_ERR			(1 << 14)
+#define INT_URX_FUL			(1 << 10)
+#define INT_URX_OV			(1 << 9)
+#define INT_QRX_FUL			(1 << 8)
+#define INT_QRX_OV			(1 << 7)
+#define INT_UQ_SYNC			(1 << 6)
+#define INT_UQ_ERR			(1 << 5)
+#define INT_RXFIFO_UNOV			(1 << 4)
+#define INT_RXFIFO_RESYNC		(1 << 3)
+#define INT_LOSS_LOCK			(1 << 2)
+#define INT_TX_EM			(1 << 1)
+#define INT_RXFIFO_FUL			(1 << 0)
+
+/* SPDIF Clock register */
+#define STC_SYSCLK_DIV_OFFSET		11
+#define STC_SYSCLK_DIV_MASK		(0x1ff << STC_TXCLK_SRC_OFFSET)
+#define STC_SYSCLK_DIV(x)		((((x) - 1) << STC_TXCLK_DIV_OFFSET) &
STC_SYSCLK_DIV_MASK)
+#define STC_TXCLK_SRC_OFFSET		8
+#define STC_TXCLK_SRC_MASK		(0x7 << STC_TXCLK_SRC_OFFSET)
+#define STC_TXCLK_SRC_SET(x)		((x << STC_TXCLK_SRC_OFFSET) &
STC_TXCLK_SRC_MASK)
+#define STC_TXCLK_ALL_EN_OFFSET		7
+#define STC_TXCLK_ALL_EN_MASK		(1 << STC_TXCLK_ALL_EN_OFFSET)
+#define STC_TXCLK_ALL_EN		(1 << STC_TXCLK_ALL_EN_OFFSET)
+#define STC_TXCLK_DIV_OFFSET		0
+#define STC_TXCLK_DIV_MASK		(0x7ff << STC_TXCLK_DIV_OFFSET)
+#define STC_TXCLK_DIV(x)		((((x) - 1) << STC_TXCLK_DIV_OFFSET) &
STC_TXCLK_DIV_MASK)
+
+/* SPDIF tx clksrc */
+enum spdif_txclk_src {
+	STC_TXCLK_SRC_0 =3D 0,
+	STC_TXCLK_SRC_1,
+	STC_TXCLK_SRC_2,
+	STC_TXCLK_SRC_3,
+	STC_TXCLK_SRC_4,
+	STC_TXCLK_SRC_5,
+	STC_TXCLK_SRC_6,
+	STC_TXCLK_SRC_7,
+};
+#define STC_TXCLK_SRC_MAX		(STC_TXCLK_SRC_7 + 1)
+#define DEFAULT_TXCLK_SRC		STC_TXCLK_SRC_1
+
+/* SPDIF tx rate */
+enum spdif_txrate {
+	SPDIF_TXRATE_32000 =3D 0,
+	SPDIF_TXRATE_44100,
+	SPDIF_TXRATE_48000,
+};
+#define SPDIF_TXRATE_MAX		(SPDIF_TXRATE_48000 + 1)
+
+
+#define SPDIF_CSTATUS_BYTE		6
+#define SPDIF_UBITS_SIZE		96
+#define SPDIF_QSUB_SIZE			(SPDIF_UBITS_SIZE / 8)
+
+
+#define FSL_SPDIF_RATES_PLAYBACK	(SNDRV_PCM_RATE_32000 |	\
+					 SNDRV_PCM_RATE_44100 |	\
+					 SNDRV_PCM_RATE_48000)
+
+#define FSL_SPDIF_RATES_CAPTURE		(SNDRV_PCM_RATE_16000 | \
+					 SNDRV_PCM_RATE_32000 |	\
+					 SNDRV_PCM_RATE_44100 | \
+					 SNDRV_PCM_RATE_48000 |	\
+					 SNDRV_PCM_RATE_64000 | \
+					 SNDRV_PCM_RATE_96000)
+
+#define FSL_SPDIF_FORMATS_PLAYBACK	(SNDRV_PCM_FMTBIT_S16_LE | \
+					 SNDRV_PCM_FMTBIT_S20_3LE | \
+					 SNDRV_PCM_FMTBIT_S24_LE)
+
+#define FSL_SPDIF_FORMATS_CAPTURE	(SNDRV_PCM_FMTBIT_S24_LE)
+
+#endif /* _FSL_SPDIF_DAI_H */
--
1.7.1
=20
=20
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