Re: [PATCH v6 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver

On Mon, Aug 19, 2013 at 02:31:47PM +0800, Bhushan Bharat-R65777 wrote:

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We here suppose the reset bit would be cleared -- "The software
reset will last
8 cycles." from RM, so if this happened to be a failure, the whole
IP module won't be normally working as well.

Also add a comment describing this against why cycle = 1000 is selected.

If it is done in 8 cycles, 1000-cycle will be surely a safe value for it.
As long as it finished in 8 cycles, it would quit anyway. Why against?

I am not against, I am saying why it was not 200 or 50 or 20 etc. I am saying that write a comment saying this much is sufficient as per specification and so keep 1000/etc as preservative.

I did't mean that. The 'against' is from

 "Also add a comment describing this 'against' why cycle = 1000 is selected."

Well, if you insist this extra comment for easy-understand, I'll add them

Thank you.
Nicolin Chen