On 07/23/2013 11:43 AM, Scott Wood wrote:

quoted

Yes. The max divider from sys clock to i2c clcok is 32K.
i2c->real_clk is the clock I2C controller pumps out, not its internal
operation clock.

32K is the max for all implementations?

Yes, according to application note 2919 (published).

BTW, Where does the "2000000" come from?  Shouldn't it be 1000000 if
you're converting to usec?  If you're trying to add some slack, say so
rather than having a comment suggest that the output of that formula is
64K cycles.  Or is there an implicit assumption that i2c runs at half
the system frequency?  Is that assumption true for all implementations
that have this erratum?

The clock source is half the sysclk. This erratum applies to selected
85xx SoCs. I have confirmed with application team that it is safe to
apply the delay to all 85xx.

quoted

quoted

In any case, you should send this patch to the i2c maintainer and list.

I don't have the name on top of my head. Is that
linux-i2c@vger.kernel.org?

Yes, and Wolfram Sang [off-list ref] is the maintainer.  This is
listed in the MAINTAINERS file.

I can resubmit this patch after the feedback is addressed.

York