Re: [PATCH 5/6 v8] iommu/fsl: Add addtional attributes specific to the PAMU driver.
From: Joerg Roedel <joro@8bytes.org>
Date: 2013-02-27 11:38:25
Also in:
linux-iommu, lkml
On Mon, Feb 18, 2013 at 06:22:18PM +0530, Varun Sethi wrote:
quoted hunk ↗ jump to hunk
Added the following domain attributes for the FSL PAMU driver: 1. Added new iommu stash attribute, which allows setting of the LIODN specific stash id parameter through IOMMU API. 2. Added an attribute for enabling/disabling DMA to a particular memory window. 3. Added domain attribute to check for PAMUV1 specific constraints. Signed-off-by: Varun Sethi <redacted> --- include/linux/iommu.h | 33 +++++++++++++++++++++++++++++++++ 1 files changed, 33 insertions(+), 0 deletions(-)diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 529987c..c44e38b 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h@@ -40,6 +40,23 @@ struct notifier_block; typedef int (*iommu_fault_handler_t)(struct iommu_domain *, struct device *, unsigned long, int, void *); +/* cache stash targets */ +#define IOMMU_ATTR_CACHE_L1 1 +#define IOMMU_ATTR_CACHE_L2 2 +#define IOMMU_ATTR_CACHE_L3 3 + +/* This attribute corresponds to IOMMUs capable of generating + * a stash transaction. A stash transaction is typically a + * hardware initiated prefetch of data from memory to cache. + * This attribute allows configuring stashig specific parameters + * in the IOMMU hardware. + */ + +struct iommu_stash_attribute { + u32 cpu; /* cpu number */ + u32 cache; /* cache to stash to: L1,L2,L3 */ +};
Please make the cache-attribute an enum instead of using defines. Joerg