Hmm, we need to work out a good abstraction for this.
On Tue, Nov 20, 2012 at 07:24:56PM +0530, Varun Sethi wrote:
Added the following domain attributes required by FSL PAMU driver:
1. Subwindows field added to the iommu domain geometry attribute.
Are the Subwindows mapped with full size or do you map only parts of the
subwindows?
+ * This attribute indicates number of DMA subwindows supported by
+ * the geometry. If there is a single window that maps the entire
+ * geometry, attribute must be set to "1". A value of "0" implies
+ * that this mechanism is not used at all(normal paging is used).
+ * Value other than* "0" or "1" indicates the actual number of
+ * subwindows.
+ */
This semantic is ugly, how about a feature detection mechanism?
quoted hunk ↗ jump to hunk
+struct iommu_stash_attribute {
+ u32 cpu; /* cpu number */
+ u32 cache; /* cache to stash to: L1,L2,L3 */
};
struct iommu_domain {@@ -60,6 +95,14 @@ struct iommu_domain {
enum iommu_attr {
DOMAIN_ATTR_MAX,
DOMAIN_ATTR_GEOMETRY,
+ /* Set the IOMMU hardware stashing
+ * parameters.
+ */
+ DOMAIN_ATTR_STASH,
+ /* Explicity enable/disable DMA for a
+ * particular memory window.
+ */
+ DOMAIN_ATTR_ENABLE,
};
When you add implementation specific attributes please add some
indication to the names that it is only for PAMU. DOMAIN_ATTR_STASH
sounds too generic.
Joerg