RE: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync

-----Original Message-----
From: Linuxppc-dev [mailto:linuxppc-dev-bounces+chenhui.zhao=3Dfreescale.=

com@lists.ozlabs.org] On Behalf

Of Kumar Gala
Sent: Friday, June 29, 2012 2:30 AM
To: Zhao Chenhui-B35336
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org list; linux-kernel@v=

ger.kernel.org list

Subject: Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase syn=

c

=20
=20
On Jun 28, 2012, at 5:50 AM, Benjamin Herrenschmidt wrote:
=20

quoted

On Thu, 2012-06-28 at 11:38 +0800, Zhao Chenhui wrote:

quoted

The bootloader have done a timebase sync. If we do not need KEXEC or
HOTPLUG_CPU feature, it is unnecessary to do it again at boot time of
kernel. I only compile the timebase sync routines
when users enable KEXEC or HOTPLUG_CPU.

Still, how much are you really saving ? Is it worth the added mess and
loss of test coverage ?

We have too many conditional stuff like that already.

Cheers,
Ben.

=20
I'd also be interested to know how long it actually takes to do time base=

 sync this way.  Since you

are freezing the timers for some period how long does it really take betw=

een the freeze/unfreeze in

mpc85xx_give_timebase()
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+	mpc85xx_timebase_freeze(1);
...
+	mpc85xx_timebase_freeze(0);
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You can use ATBL/U as a way to see # of cycles taken.
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- k

I measured it using ATBL on MPC8572DS with 1.5GHz core frequency and 600MHz=
 CCB frequency.
The average of 10 times is 1019 clock. It seems that most of the time spent=
 by isync and msync.

-Chenhui