On Sat, Feb 25, 2012 at 12:47 AM, Yinghai Lu [off-list ref] wrote:

On Fri, Feb 24, 2012 at 2:24 PM, Jesse Barnes [off-list ref] =

wrote:

quoted

On Thu, 23 Feb 2012 12:51:30 -0800
Bjorn Helgaas [off-list ref] wrote:

quoted

2) We already have a way to add resources to a root bus: the
pci_add_resource() used to add I/O port and MMIO apertures. =A0I think
it'd be a lot simpler to just use that same interface for the bus
number aperture, e.g.,

=A0 =A0 pci_add_resource(&resources, hose->io_space);
=A0 =A0 pci_add_resource(&resources, hose->mem_space);
=A0 =A0 pci_add_resource(&resources, hose->busnr_space);
=A0 =A0 bus =3D pci_scan_root_bus(dev, next_busno, pci_ops, sysdata, &r=

esources);

quoted

quoted

This is actually a bit redundant, since "next_busno" should be the
same as hose->busnr_space->start. =A0So if we adopted this approach, we
might want to eventually drop the "next_busno" argument.

Yeah that would be nice, the call would certainly make more sense that
way.

no, I don't think so.

using pci_add_resource will need to create dummy resource abut bus range.

I don't see the problem here.  The bus number aperture is a
fundamental property of a host bridge, and any firmware or native
bridge driver that tells you about a bridge but doesn't tell you the
bus number aperture is just broken.

Every arch already has struct resources for the MMIO and IO port
regions available on the bus.  ACPI already has a resource for the bus
number range.  It makes sense to me that the arch should supply a bus
number resource.

Conceptually, it's just like the MMIO and IO resources, so it makes
sense to me that the code for bus numbers should look like the code
for MMIO and IO ports.

there is lots of pci_scan_root_bus(), =A0and those user does not bus end
yet before scan.
so could just hide pci_insert_busn_res in pci_scan_root_bus, and
update busn_res end there.

pci_scan_child_bus() does NOT tell you the end of the bus number
aperture, and we shouldn't pretend that it does.  It might give you a
lower bound on the end of the aperture (as long as you're willing to
trust the current PCI config and you don't change anything).

other arch like x86, ia64, powerpc, sparc, will insert exact bus range
between pci_create_root_bus and
pci_scan_child_bus, will not need to update busn_res end.

please check v7 of this patchset.

=A0 =A0 =A0 =A0git://git.kernel.org/pub/scm/linux/kernel/git/yinghai/linu=

x-yinghai.git

for-pci-busn-alloc

I looked at your git tree, but I can't tell whether what's there is v7
or not and it's too much trouble to try to figure it out.

Bjorn