Re: [PATCH 09/24] PCI, powerpc: Register busn_res for root buses

On Wed, Feb 8, 2012 at 7:58 AM, Bjorn Helgaas [off-list ref] wrote:

On Sat, Feb 4, 2012 at 10:57 PM, Yinghai Lu [off-list ref] wrote:

quoted

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <redacted>
Cc: linuxppc-dev@lists.ozlabs.org
---
=A0arch/powerpc/kernel/pci-common.c | =A0 =A07 ++++++-
=A01 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-=

common.c

quoted

index cce98d7..501f29b 100644

--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c

@@ -1732,6 +1732,8 @@ void __devinit pcibios_scan_phb(struct pci_control=

ler *hose)

quoted

=A0 =A0 =A0 =A0bus->secondary =3D hose->first_busno;
=A0 =A0 =A0 =A0hose->bus =3D bus;

+ =A0 =A0 =A0 pci_bus_insert_busn_res(bus, hose->first_busno, hose->last=

_busno);

quoted

+
=A0 =A0 =A0 =A0/* Get probe mode and perform scan */
=A0 =A0 =A0 =A0mode =3D PCI_PROBE_NORMAL;
=A0 =A0 =A0 =A0if (node && ppc_md.pci_probe_mode)

@@ -1742,8 +1744,11 @@ void __devinit pcibios_scan_phb(struct pci_contro=

ller *hose)

quoted

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0of_scan_bus(node, bus);
=A0 =A0 =A0 =A0}

- =A0 =A0 =A0 if (mode =3D=3D PCI_PROBE_NORMAL)
+ =A0 =A0 =A0 if (mode =3D=3D PCI_PROBE_NORMAL) {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 pci_bus_update_busn_res_end(bus, 255);
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0hose->last_busno =3D bus->subordinate =3D=

 pci_scan_child_bus(bus);

quoted

+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 pci_bus_update_busn_res_end(bus, bus->subo=

rdinate);

quoted

+ =A0 =A0 =A0 }

The only architecture-specific thing here is discovering the range of
bus numbers below a host bridge. =A0The architecture should not have to
mess around with pci_bus_update_busn_res_end() like this. =A0It should
be able to say "here's my bus number range" (and of course the PCI
core can default to 0-255 if the arch doesn't supply a range) and the
core should take care of the rest.

during the pci_scan_child_bus,  child bus busn_res will be inserted
under parent bus busn_res.

So need to make sure parent busn_res.end is bigger enough.


Yinghai