Re: [RFC] Inter-processor Mailboxes Drivers

From: ext Linus Walleij <redacted>
Subject: Re: [RFC] Inter-processor Mailboxes Drivers
Date: Mon, 14 Feb 2011 09:39:32 +0100

On Mon, Feb 14, 2011 at 8:32 AM, Hiroshi DOYU [off-list ref] wrote:

quoted

OMAP mailbox is the interrupt driven 32bit unit H/W FIFO to other
cores.

How is it used? Is it a low-traffic (like single 32bit words etc) signal
control-path link while the actual high-throughput data-path is done
with shared memory? (That is how the db5500 mbox works anyways.)

Yes, maybe quite similar.

maibox is not single 32 bit but is 32 bit x 4(or 8?) slots fifo, IIRC,
and mainly it is used as notification between cores. And big amount of
data is transftered with sahred memory, which has been mapped onto the
virtual address space of the other side of core, in advance.

For example, typical usage of DSP, mp3 decoding,

1, ARM maps 2 shared memory area(input/output) onto DSP virtual
   address space.
2, ARM fills mp3 data in input buffer.
3, ARM notifies DSP that data is ready in input buffer.
4, DSP decodes input data and put output data on output buffer.
5, DSP notifies that output buffer is ready.

Roughly something like the above. DSP S/W is multi-tasking, though.

Does db5500 use IOMMU for mapping shared memories?