On Sep 17, 2010, at 1:36 AM, Chris Friesen wrote:

On 09/16/2010 11:33 PM, Benjamin Herrenschmidt wrote:

quoted

On Fri, 2010-09-17 at 00:17 -0500, Kumar Gala wrote:

quoted

Not sure how the 970 bit worked, but this seems a bit problematic =

for

quoted

quoted

switching between kernel and application for how we do this on
e500mc/e5500.  We'd have to touch the control bit on every exception
path which seems ugly to me.

=20
Unless the kernel uses dcbzl (feature fixup replacement ?)
=20
In that case it's on context switch only.

=20
This is basically what we did.  Kernel and system libraries (glibc and
friends) always use dcbzl, process flag indicates compatibility, touch
the control bit on task context switch if the prev and next processes
have different compatibility modes.
=20
On the 970 you have to invalidate the entire icache whenever you =

change

the control bit.  This is a pain involving a loop that calls icbi on =

512

cachelines.

I'm pretty sure on e500mc / e5500 you only need proper sync/isync/msync =
after the change in the control register.

- k=