On 09/16/2010 03:39 PM, Scott Wood wrote:

On Thu, 16 Sep 2010 14:06:37 -0600
Chris Friesen [off-list ref] wrote:

quoted

We're looking at maybe doing some work with an e5500-based system.  Is
there any support existing/planned for this core?

Check with whoever you'd be getting the hardware from about a BSP.

And yes, it should be supported upstream at some point.

We haven't settled on a vendor yet, so I was just wondering in general
what the story was around support.

quoted

Also, do we know what the cache line size is--we have some legacy apps
that assume 32-byte.

The cache line is 64 bytes.  As with e500mc, there is a "dcbz32" mode
for compatibility, though you probably lose much of the performance
benefit of dcbz, and it might upset other software that properly checks
for the cache line size but doesn't use dcbzl.

Right.  We currently use a 970-series cpu and have implemented a
per-process flag to indicate whether 32-byte mode is needed or not.
We'd have to do something similar with the new cpu.

One last question--can you comment on the speed of an e5500 relative to
a 970 for integer operations?

Thanks,

Chris


-- 
Chris Friesen
Software Developer
GENBAND
chris.friesen@genband.com
www.genband.com