On Wed, Jun 9, 2010 at 10:32 AM, Mark Brown
[off-list ref] wrote:

On Wed, Jun 09, 2010 at 10:21:40AM -0400, Eric Millbrandt wrote:

[Please fix your MUA to word wrap paragraphs to within 80 characters,
I've reflowed the text below.]

quoted

From the MPC5200B user manual:
"Some AC97 devices goes to a test mode, if the Sync line is high
during the Res line is low (reset phase). To avoid this behavior the
Sync line must be also forced to zero during the reset phase. To do
that, the pin muxing should switch to GPIO mode and the GPIO control
register should be used to control the output lines."

Please include this quote in the changelog for the patch, if this a
documented workaround from the vendor that's a very different thing to
something that you've found happens to work on your systems (which is
more what your changelog sounded like).

Mark, is there a way to ask the chip if it is in test mode? We need to
be sure that's whats happening and it isn't some other glitch.


-- 
Jon Smirl
jonsmirl@gmail.com