RE: [PATCH][v1] powerpc/85xx: Create dts for each core in CAMPmodefor P2020RDB

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-----Original Message-----
From: Gabriel Paubert [mailto:paubert@iram.es]=20
Sent: Thursday, September 10, 2009 9:33 PM
To: Aggrwal Poonam-B10812
Cc: linuxppc-dev@ozlabs.org
Subject: Re: [PATCH][v1] powerpc/85xx: Create dts for each=20
core in CAMPmodefor P2020RDB
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On Thu, Sep 10, 2009 at 08:48:38PM +0530, Aggrwal Poonam-B10812 wrote:

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-----Original Message-----
From: Gabriel Paubert [mailto:paubert@iram.es]
Sent: Thursday, September 10, 2009 3:03 PM
To: Aggrwal Poonam-B10812
Cc: linuxppc-dev@ozlabs.org
Subject: Re: [PATCH][v1] powerpc/85xx: Create dts for=20

each core in=20

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CAMPmode for P2020RDB
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On Thu, Sep 10, 2009 at 02:27:11PM +0530, Poonam Aggrwal wrote:

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This patch creates the dts files for each core and splits

the devices

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between the two cores for P2020RDB.
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core0 has memory, L2, i2c, spi, dma1, usb, eth0, eth1, crypto,=20
global-util, pci0
core1 has L2, dma2, eth0, pci1, msi.

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Surely you mean eth1 and eth2 for core0, no?

Yes you are right , I'll fix this.

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At least it's what I gather from the code.
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Also both cores have a node called serial0, at different=20

addresses=20

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but with the same interrupt!

Yes both the UARTS use the same int line in shared mode.=20

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But in the mpic comment line there is "serial1", and=20

interrupt 42 is=20

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the only number which appears in both lists of mpic protected=20
interrupts.

I am not sure how to handle the shared interrupts in AMP scenario,=20
although this has been tested and both serials are working=20

one on each=20

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core.

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Ok, I wrongly understood protected interrupts as reserved for=20
one core. However, I still dislike two devices having the same name.
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Otherwise it may work if every interrupt is delivered to both=20
cores although statistically only one core will actually have=20
some work to do. Doesn't the kernel complain about unhandled=20
irqs however?=20
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We don't see any such messages of unhandled interrupts, although I
checked the corresponding files for mpc8572ds, they do not have the
interrupts property for the serial ports at all, in both the core0 and
core1 dts.
Don't know the reason.

	Regards,
	Gabriel
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+
+		serial0: serial@4500 {
+			cell-index =3D <0>;
+			device_type =3D "serial";
+			compatible =3D "ns16550";
+			reg =3D <0x4500 0x100>;
+			clock-frequency =3D <0>;
+			interrupts =3D <42 2>;
+			interrupt-parent =3D <&mpic>;
+		};

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+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells =3D <0>;
+			#interrupt-cells =3D <2>;
+			reg =3D <0x40000 0x40000>;
+			compatible =3D "chrp,open-pic";
+			device_type =3D "open-pic";
+			protected-sources =3D <
+			42 76 77 78 79 /* serial1 , dma2 */
+			29 30 34 26 /* enet0, pci1 */
+			0xe0 0xe1 0xe2 0xe3 /* msi */
+			0xe4 0xe5 0xe6 0xe7
+			>;
+		};
+
+

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+		serial0: serial@4600 {
+			cell-index =3D <1>;
+			device_type =3D "serial";
+			compatible =3D "ns16550";
+			reg =3D <0x4600 0x100>;
+			clock-frequency =3D <0>;
+			interrupts =3D <42 2>;
+			interrupt-parent =3D <&mpic>;
+		};
+
+

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+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells =3D <0>;
+			#interrupt-cells =3D <2>;
+			reg =3D <0x40000 0x40000>;
+			compatible =3D "chrp,open-pic";
+			device_type =3D "open-pic";
+			protected-sources =3D <
+			17 18 43 42 59 47 /*ecm, mem,=20

i2c, serial0, spi,gpio */

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+			16 20 21 22 23 28 	/* L2,=20

dma1, USB */

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+			03 35 36 40 31 32 33 	/*=20

mdio, enet1, enet2 */

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+			72 45 58 25 		/*=20

sdhci, crypto , pci */

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+			>;
+		};
+

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