Thread (16 messages) 16 messages, 3 authors, 2009-08-31

RE: [PATCH v2] powerpc/85xx: Add eSDHC support for MPC8536DS boards

From: Hu Mingkai-B21284 <hidden>
Date: 2009-08-31 07:51:53
Also in: lkml

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-----Original Message-----
From: Anton Vorontsov [mailto:avorontsov@ru.mvista.com]=20
Sent: Friday, August 28, 2009 11:20 PM
To: Hu Mingkai-B21284
Cc: Kumar Gala; Ben Dooks; linux-kernel@vger.kernel.org;=20
sdhci-devel@lists.ossman.eu; linuxppc-dev@ozlabs.org; Andrew=20
Morton; Pierre Ossman; David Vrabel
Subject: Re: [PATCH v2] powerpc/85xx: Add eSDHC support for=20
MPC8536DS boards
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On Fri, Aug 28, 2009 at 07:02:51PM +0800, Hu Mingkai-B21284 wrote:
quoted
quoted
On Tue, Aug 18, 2009 at 08:24:17PM -0500, Kumar Gala wrote:
quoted
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On Aug 18, 2009, at 6:38 PM, Anton Vorontsov wrote:
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quoted
This patch simply adds sdhci node to the device tree.

We specify clock-frequency manually, so that eSDHC will
work without
quoted
quoted
upgrading U-Boot. Though, that'll only work for default setup=20
(1500
MHz) on new board revisions. For non-default setups, it's
recommended
quoted
quoted
to upgrade U-Boot, since it will fixup clock-frequency
automatically.
quoted
quoted
Signed-off-by: Anton Vorontsov <redacted>
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out of interest the 85xx eSDHC don't need the sdhci,wp-inverted=20
property?
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Yes, eSDHC controllers in MPC85xx report normal state in its=20
registers.
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Hi Anton,
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The eSDHC controller in different silicon version on=20
MPC8536  reports=20
quoted
different WP state in the register PRSSTAT:
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Thanks a million for the heads up!
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Yes, the manual I used ("MPC8536ERM Rev. 0 10/2008") doesn't=20
mention that, but the newer manual that I just downloaded=20
("MPC8536ERM Rev. 1
05/2009") does.
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[...]
quoted
For silicon 1.0,  the macro=20
SDHCI_QUIRK_INVERTED_WRITE_PROTECT is also=20
quoted
defined, so the dirver will report the error WP state in function=20
sdhci_get_ro.
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Not any longer. We don't actually define it for any 85xx CPUs.
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I need to think how should we handle all these WP inversions. :-)
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So, we have inversion in BCSR (depending on the BCSR=20
revision), configurable inversion in CPU via GENCFGR for 1.1=20
silicon, and non-configurable non-inverted reporting for 1.0=20
silicon...
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Do you know if there are any plans to fix the WP inversion=20
for MPC8569E-MDS boards, or make something like GENCFGR for=20
MPC8569 CPUs?
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Thanks,
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Sorry, I also don't know the plan to MPC8569 CPU, but if I get any info,
I'll inform you ASAP. :-)

Best regards,
Mingkai
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
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