RE: [PATCH v2] powerpc/85xx: Add eSDHC support for MPC8536DS boards
From: Hu Mingkai-B21284 <hidden>
Date: 2009-08-31 07:51:53
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-----Original Message----- From: Anton Vorontsov [mailto:avorontsov@ru.mvista.com]=20 Sent: Friday, August 28, 2009 11:20 PM To: Hu Mingkai-B21284 Cc: Kumar Gala; Ben Dooks; linux-kernel@vger.kernel.org;=20 sdhci-devel@lists.ossman.eu; linuxppc-dev@ozlabs.org; Andrew=20 Morton; Pierre Ossman; David Vrabel Subject: Re: [PATCH v2] powerpc/85xx: Add eSDHC support for=20 MPC8536DS boards =20 On Fri, Aug 28, 2009 at 07:02:51PM +0800, Hu Mingkai-B21284 wrote:quoted
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On Tue, Aug 18, 2009 at 08:24:17PM -0500, Kumar Gala wrote:quoted
=20 On Aug 18, 2009, at 6:38 PM, Anton Vorontsov wrote: =20quoted
This patch simply adds sdhci node to the device tree. We specify clock-frequency manually, so that eSDHC willwork withoutquoted
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upgrading U-Boot. Though, that'll only work for default setup=20 (1500 MHz) on new board revisions. For non-default setups, it'srecommendedquoted
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to upgrade U-Boot, since it will fixup clock-frequencyautomatically.quoted
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Signed-off-by: Anton Vorontsov <redacted>=20 out of interest the 85xx eSDHC don't need the sdhci,wp-inverted=20 property?=20 Yes, eSDHC controllers in MPC85xx report normal state in its=20 registers. =20=20 Hi Anton, =20 The eSDHC controller in different silicon version on=20MPC8536 reports=20quoted
different WP state in the register PRSSTAT:=20 Thanks a million for the heads up! =20 Yes, the manual I used ("MPC8536ERM Rev. 0 10/2008") doesn't=20 mention that, but the newer manual that I just downloaded=20 ("MPC8536ERM Rev. 1 05/2009") does. =20 [...]quoted
For silicon 1.0, the macro=20SDHCI_QUIRK_INVERTED_WRITE_PROTECT is also=20quoted
defined, so the dirver will report the error WP state in function=20 sdhci_get_ro.=20 Not any longer. We don't actually define it for any 85xx CPUs. =20 I need to think how should we handle all these WP inversions. :-) =20 So, we have inversion in BCSR (depending on the BCSR=20 revision), configurable inversion in CPU via GENCFGR for 1.1=20 silicon, and non-configurable non-inverted reporting for 1.0=20 silicon... =20 Do you know if there are any plans to fix the WP inversion=20 for MPC8569E-MDS boards, or make something like GENCFGR for=20 MPC8569 CPUs? =20 Thanks, =20
Sorry, I also don't know the plan to MPC8569 CPU, but if I get any info, I'll inform you ASAP. :-) Best regards, Mingkai
-- Anton Vorontsov email: cbouatmailru@gmail.com irc://irc.freenode.net/bd2 =20 =20