On Fri, Aug 28, 2009 at 07:02:51PM +0800, Hu Mingkai-B21284 wrote:

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On Tue, Aug 18, 2009 at 08:24:17PM -0500, Kumar Gala wrote:

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On Aug 18, 2009, at 6:38 PM, Anton Vorontsov wrote:

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This patch simply adds sdhci node to the device tree.

We specify clock-frequency manually, so that eSDHC will 

work without 

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upgrading U-Boot. Though, that'll only work for default setup (1500
MHz) on new board revisions. For non-default setups, it's 

recommended 

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to upgrade U-Boot, since it will fixup clock-frequency 

automatically.

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Signed-off-by: Anton Vorontsov <redacted>

out of interest the 85xx eSDHC don't need the sdhci,wp-inverted 
property?

Yes, eSDHC controllers in MPC85xx report normal state in its 
registers.

Hi Anton,

The eSDHC controller in different silicon version on MPC8536  reports
different WP state in the register PRSSTAT:

Thanks a million for the heads up!

Yes, the manual I used ("MPC8536ERM Rev. 0 10/2008") doesn't mention
that, but the newer manual that I just downloaded ("MPC8536ERM Rev. 1
05/2009") does.

[...]

For silicon 1.0,  the macro SDHCI_QUIRK_INVERTED_WRITE_PROTECT is also
defined,
so the dirver will report the error WP state in function sdhci_get_ro.

Not any longer. We don't actually define it for any 85xx CPUs.

I need to think how should we handle all these WP inversions. :-)

So, we have inversion in BCSR (depending on the BCSR revision),
configurable inversion in CPU via GENCFGR for 1.1 silicon, and
non-configurable non-inverted reporting for 1.0 silicon...

Do you know if there are any plans to fix the WP inversion for
MPC8569E-MDS boards, or make something like GENCFGR for MPC8569
CPUs?

Thanks,

-- 
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2