=

-----Original Message-----
From: Grant Likely [mailto:grant.likely@secretlab.ca] =

Sent: Thursday, April 09, 2009 8:35 AM
To: Roderick Colenbrander
Cc: Josh Boyer; linux-fbdev-devel@lists.sourceforge.net; =

adaplas@gmail.com; Suneel Garapati; linuxppc-dev@ozlabs.org; =

akonovalov@ru.mvista.com; John Linn
Subject: Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB =

support (non-DCR)
=

On Thu, Apr 9, 2009 at 7:06 AM, Roderick Colenbrander
[off-list ref] wrote:

quoted

On Thu, Apr 9, 2009 at 2:46 PM, Josh Boyer =

[off-list ref]

quoted

wrote:

quoted

On Wed, Apr 08, 2009 at 03:11:25PM -0600, John Linn wrote:

quoted

From: Suneel <[mailto:suneel.garapati@xilinx.com]>

Added support for the new xps tft controller.

The new core has PLB interface support in addition to existing
DCR interface.

The driver has been modified to support this new core which
can be connected on PLB or DCR bus.

Signed-off-by: Suneel <redacted>
Signed-off-by: John Linn <redacted>
---
drivers/video/xilinxfb.c | =A0227
++++++++++++++++++++++++++++++++--------------
1 files changed, 160 insertions(+), 67 deletions(-)

diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index a82c530..a28a834 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c

@@ -1,17 +1,24 @@

/*
- * xilinxfb.c
=A0*
- * Xilinx TFT LCD frame buffer driver
+ * Xilinx TFT frame buffer driver
=A0*
=A0* Author: MontaVista Software, Inc.
=A0* =A0 =A0 =A0 =A0 source@mvista.com
=A0*
=A0* 2002-2007 (c) MontaVista Software, Inc.
=A0* 2007 (c) Secret Lab Technologies, Ltd.
+ * 2009 (c) Xilinx Inc.
=A0*
- * This file is licensed under the terms of the GNU =

General Public

quoted

quoted

quoted

License
- * version 2. =A0This program is licensed "as is" without =

any warranty of

quoted

quoted

quoted

any
- * kind, whether express or implied.
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms of the GNU General Public
+ * License as published by the Free Software Foundation;
+ * either version 2 of the License, or (at your option) any
+ * later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
=A0*/

What Stephen said.

quoted

#define NUM_REGS =A0 =A0 =A02
#define REG_FB_ADDR =A0 0

@@ -112,6 +123,11 @@ struct xilinxfb_drvdata {

=A0 =A0 =A0 struct fb_info =A0info; =A0 =A0 =A0 =A0 =A0 /* FB driver=

 info record */

quoted

quoted

quoted

+ =A0 =A0 =A0u32 =A0 =A0 =A0 =A0 =A0 =A0 regs_phys; =A0 =A0 =A0/* phy=

s. address =

of the control

quoted

quoted

quoted

+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0registers */

quoted

quoted

Is this driver usable on the 440 based Xilinx devices? =A0If =

so, is it

quoted

quoted

possible
to have the physical address of the registers above 4GiB, =

so is common

quoted

quoted

with
almost all the I/O on the other 440 boards?

The driver works fine on 440 based Xilinx boards (the ML510 =

I use has a 440

quoted

core). It might be nice to move physical addresses above =

4GB for devices but

quoted

in all Xilinx tools and reference designs addresses below =

4GB are used for

quoted

periperhals and I think even below 2GB (or even below 1GB). =

It depends on

quoted

the design.

=

Regardless, it is good practice to use phys_addr_t instead of u32 for
physical addresses.
=

I can change that when I respin to incorporate comments.

Thanks,
John

g.
=

-- =

Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
=

=

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