Re: cpm_dpalloc questions

bhanu jampala wrote:

I am working on MCC HDLC controller on MCC8260. I have two important questions:

1. What is the range of DPRAM from which the cpm_dpalloc allocates memory?
    How does the cpm_dpalloc work?

Assuming you're using arch/powerpc on a recent kernel version, it allocates from the memory specified in the muram node of the device tree.

    I need this because, I need to reserve the DPRAM memory for MCC2
from (128 * 60) to (255 * 60)
    for channels ranging from 128 - 255.

Why do you need to reserve a specific address?

2. PROFF_SMC1 pointer placed at 0 , 64 offsets. is this not an area of
MCC1 controller?

No, MCC1 PRAM starts at offset 0x8700.  Any other areas used are under software control.

    how if I want to use the MCC channel on MCC1.

 In file include/asm-powerpc/cpm2.h.

 /* The SMCs are relocated to any of the first eight DPRAM pages.
  * We will fix these at the first locations of DPRAM, until we
  * get some microcode patches :-).
  * The parameter ram space for the SMCs is fifty-some bytes, and
  * they are required to start on a 64 byte boundary.
  */
 #define PROFF_SMC1      (0)
 #define PROFF_SMC2      (64)

This is obsolete arch/ppc stuff and should be removed; the SMC pram is now dynamically allocated and relocated (and before that, it came from the device tree).

-Scott