cpm_dpalloc questions

Hi Guys,

I am working on MCC HDLC controller on MCC8260. I have two important questions:

1. What is the range of DPRAM from which the cpm_dpalloc allocates memory?
    How does the cpm_dpalloc work?
    I need this because, I need to reserve the DPRAM memory for MCC2
from (128 * 60) to (255 * 60)
    for channels ranging from 128 - 255.

2. PROFF_SMC1 pointer placed at 0 , 64 offsets. is this not an area of
MCC1 controller?
    how if I want to use the MCC channel on MCC1.

 In file include/asm-powerpc/cpm2.h.

 /* The SMCs are relocated to any of the first eight DPRAM pages.
  * We will fix these at the first locations of DPRAM, until we
  * get some microcode patches :-).
  * The parameter ram space for the SMCs is fifty-some bytes, and
  * they are required to start on a 64 byte boundary.
  */
 #define PROFF_SMC1      (0)
 #define PROFF_SMC2      (64)

Regards,
Adams

bhanu jampala wrote:

I am working on MCC HDLC controller on MCC8260. I have two important questions:

1. What is the range of DPRAM from which the cpm_dpalloc allocates memory?
    How does the cpm_dpalloc work?

Assuming you're using arch/powerpc on a recent kernel version, it allocates from the memory specified in the muram node of the device tree.

    I need this because, I need to reserve the DPRAM memory for MCC2
from (128 * 60) to (255 * 60)
    for channels ranging from 128 - 255.

Why do you need to reserve a specific address?

2. PROFF_SMC1 pointer placed at 0 , 64 offsets. is this not an area of
MCC1 controller?

No, MCC1 PRAM starts at offset 0x8700.  Any other areas used are under software control.

    how if I want to use the MCC channel on MCC1.

 In file include/asm-powerpc/cpm2.h.

 /* The SMCs are relocated to any of the first eight DPRAM pages.
  * We will fix these at the first locations of DPRAM, until we
  * get some microcode patches :-).
  * The parameter ram space for the SMCs is fifty-some bytes, and
  * they are required to start on a 64 byte boundary.
  */
 #define PROFF_SMC1      (0)
 #define PROFF_SMC2      (64)

This is obsolete arch/ppc stuff and should be removed; the SMC pram is now dynamically allocated and relocated (and before that, it came from the device tree).

-Scott

Hi Scott,

No, MCC1 PRAM starts at offset 0x8700.  Any other areas used are under
software control.

Yes, you are right. But, I was refereing to MCC channel specific HDLC
parameters.

Reason: I am using the MCC2 which uses memory from offset 0x2000 to
0x4000 for Chan Specific parameters.
you can see that in MCC chapter i.e. 29.3.1 on a MPC8280 manual.
(channel specific HDLC parameters)

I need to make sure that cpm_dpalloc is not using this part of DPRAM
to allocate memory.
I just wanne make sure no other device driver that use cpm_dpalloc to
allocate memory for their BDs i.e. scc, smc, fcc.

and it looks to me like it is allocating me memory starting from 0x128 or 0x400.

This is obsolete arch/ppc stuff and should be removed; the SMC pram is now
dynamically allocated and relocated (and before that, it came from the
device tree).

Yes, I am using 2.6.19.2. I am right now in the middle of finalizing
the BSP port. So, I cannot move on further to device trees. I will
doing that stuff with in a month but now I am with 2.6.19.2.

Regards,
Adams

Hi Guys,

Figured out that cpm_dpalloc is doing the memory allocation in the
range of  0x0000 - 0x3EFEC.
I tried to dig in and figured out that it is really not affecting me
as the memory address I dont wanted to be touched is 0x2000.
and existing drivers fcc and scc allocate memory at boot time and and
it is something range of ix100 -0x200.
so, no problem.

- mukund

On Thu, Aug 28, 2008 at 1:03 PM, bhanu jampala [off-list ref] wrote:

Hi Scott,

quoted

No, MCC1 PRAM starts at offset 0x8700.  Any other areas used are under
software control.

Yes, you are right. But, I was refereing to MCC channel specific HDLC
parameters.

Reason: I am using the MCC2 which uses memory from offset 0x2000 to
0x4000 for Chan Specific parameters.
you can see that in MCC chapter i.e. 29.3.1 on a MPC8280 manual.
(channel specific HDLC parameters)

I need to make sure that cpm_dpalloc is not using this part of DPRAM
to allocate memory.
I just wanne make sure no other device driver that use cpm_dpalloc to
allocate memory for their BDs i.e. scc, smc, fcc.

and it looks to me like it is allocating me memory starting from 0x128 or 0x400.

quoted

This is obsolete arch/ppc stuff and should be removed; the SMC pram is now
dynamically allocated and relocated (and before that, it came from the
device tree).

Yes, I am using 2.6.19.2. I am right now in the middle of finalizing
the BSP port. So, I cannot move on further to device trees. I will
doing that stuff with in a month but now I am with 2.6.19.2.

Regards,
Adams