Re: ARCH=ppc -> ARCH=powerpc : help needed for dts file
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From: Philippe De Muyter <hidden>
Date: 2008-03-05 23:34:33
Hi Ben, On Thu, Mar 06, 2008 at 07:14:28AM +1100, Benjamin Herrenschmidt wrote:
On Wed, 2008-03-05 at 17:15 +0100, Philippe De Muyter wrote:quoted
I asked the guy who designed the hardware, and if I understand correctly : - the i/o and memory resources of the pci device are connected to the pci bus - the interrupts are directly connected to the MPIC Can I describe that in the dts file ?Sure, you can describe pretty much any interrupt routing, provided that we know -how- (ie. where) they are connected. We also need to know the
They are connected directly to the pic-part of the mpc8540 just as described in the .c file in the other mail.
idsel of the devices. (The later we can deduce from lspci done in arch/ppc).
Does this (boot error messages in the not-working arch/powerpc kernel) : PCI: Cannot allocate resource region 0 of device 0000:00:12.0 PCI: Cannot allocate resource region 0 of device 0000:00:12.1 PCI: Cannot allocate resource region 0 of device 0000:00:12.2 PCI: Cannot allocate resource region 1 of device 0000:00:12.2 or this (/proc/bus/pci in the working arch/pcc kernel) Sorry, I am at home now and cannot access my board :) or this (boot info messages from working arch/pcc kernel) : ohci1394: fw-host0: OHCI-1394 1.1 (PCI): IRQ=[55] MMIO=[9f7fd800-9f7fdfff] Max Packet=[2048] IR/IT contexts=[4/8] ... Yenta: CardBus bridge found at 0000:00:12.0 [0000:0000] ... Yenta TI: socket 0000:00:12.0, mfunc 0x00001b00, devctl 0x66 Yenta TI: socket 0000:00:12.0 probing PCI interrupt failed, trying to fix Yenta TI: socket 0000:00:12.0 falling back to parallel PCI interrupts Yenta TI: socket 0000:00:12.0 parallel PCI interrupts ok Yenta: ISA IRQ mask 0x0000, PCI irq 53 ... pccard: PCMCIA card inserted into slot 0 cs: memory probe 0x80000000-0x9fffffff: excluding 0x80000000-0x807fffff 0x9f000000-0x9fffffff pcmcia: registering new device pcmcia0.0 Yenta TI: socket 0000:00:12.1 parallel PCI interrupts ok Yenta: ISA IRQ mask 0x0000, PCI irq 54 Socket status: 30000086 or this (U-boot info message) : PCI Scan: Found Bus 0, Device 18, Function 0 00 12 104c ac46 0607 ff PCI Scan: Found Bus 0, Device 18, Function 1 00 12 104c ac46 0607 ff PCI Scan: Found Bus 0, Device 18, Function 2 00 12 104c 802a 0c00 00 and this (/proc/interrupts on a working system) CPU0 25: 0 OpenPIC Level gfar_interrupt 26: 245 OpenPIC Level serial 27: 0 OpenPIC Level i2c-mpc 53: 18797 OpenPIC Level yenta, ide0 54: 1 OpenPIC Level yenta 55: 79 OpenPIC Level ohci1394 BAD: 0 help ? Philippe
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Or are you doing some swizzling ? Also, I would need to know how those external IRQs are connected tothe MPIC,quoted
I don't have the spec of that chip here. Hrm. Somebody fromfreescale canquoted
help him here ? It's also not clear to me what your interrupts 9 10 and 11 are sinceyouquoted
seem to only talk about PIRQA...D which is only 4 lines .. So at this stage, that's not enough information. We need to knowexactly howquoted
you have wired things on your board, and somebody from fsl needs totellquoted
me how the ExtIrq are routed to the MPIC on that guy. Once that's done, you seem to have grasped the interrupt map... foranyquoted
device or slot, you provide the mapping between idsel/pirq line onone side,quoted
and mpic interrupt & sense on the other. For PCI, sense is always 1for anquoted
mpic so you mostly have to check your actual MPIC source numbers.quoted
From your .dts, I see you've been doing some swizzling of slotsusingquoted
interrupts 1...4 ... do that correspond to EXTIRQ 5....8 ? Ben.quoted
/************************************************************************* */quoted
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--- ./arch/ppc/platforms/85xx/mpc85xx_ads_common.hbk 2008-01-2422:58:37.000000000 +0000quoted
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+++ ./arch/ppc/platforms/85xx/mpc85xx_ads_common.h 2008-02-2016:36:07.000000000 +0000quoted
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@@ -29,10 +29,17 @@ extern void mpc85xx_ads_map_io(void) __init; /* PCI interrupt controller */ +#ifdef CONFIG_MEIP_8540 +#define PIRQA MPC85xx_IRQ_EXT5 +#define PIRQB MPC85xx_IRQ_EXT6 +#define PIRQC MPC85xx_IRQ_EXT7 +#define PIRQD MPC85xx_IRQ_EXT8 +#else #define PIRQA MPC85xx_IRQ_EXT1 #define PIRQB MPC85xx_IRQ_EXT2 #define PIRQC MPC85xx_IRQ_EXT3 #define PIRQD MPC85xx_IRQ_EXT4 +#endif #define MPC85XX_PCI1_LOWER_IO 0x00000000 #define MPC85XX_PCI1_UPPER_IO 0x00ffffff