On Nov 16, 2007 3:44 PM, robert lazarski [off-list ref] wrote:

On Nov 16, 2007 10:27 AM, Clemens Koller [off-list ref] wrote:

quoted

The SRESET# (pin AF20) is the soft reset input, causes
an mcp assertion to the core.... (RTFM)

That's what we are doing. The 85xx docs say "Soft reset. Causes a
machine check interrupt to the e500 core. Note that if the e500 core
is not configured to process machine check interrupts, the assertion
of SRESET causes a core checkstop. SRESET need not be asserted during
a hard reset."

Sorry for replying to myself, but thought I'd mention SRESET works
fine on 85xx 2.6.23 , ie, the board resets after kernel panic. It
doesn't work for me on 2.6.24rc2 .

Robert