Re: PCI IRQ -MPC8540
From: Steve Iribarne (GMail) <hidden>
Date: 2007-01-17 00:29:59
Is this the pin used for the external messaging? On 1/16/07, agnel juni [off-list ref] wrote:
Hello all: I would like to understand if there is a way to program the PCI interrupt pin register of MPC8540. I did look for this in the datasheet, but couldn't find any positive answer. Currently, I am working in a set-up where MPC8540 is an agent, plugged into the PC host. I couldn't get an IRQ for the card when plugged in some PCI slots, whereas in one of the slots I do see a non-zero value. It would be great if you could help me understand the issue. I am sorry if the question is inapporpriate in the group. I am desperate to solve the issue. Thanks for any help. J.Joseph ----- Original Message ---- From: Kumar Gala <redacted> To: Wang Matthew-R59995 <redacted> Cc: linuxppc-embedded@ozlabs.org Sent: Wednesday, 18 October, 2006 6:54:24 PM Subject: Re: Linuxppc-embedded Digest, Vol 26, Issue 36 On Oct 18, 2006, at 8:10 PM, Wang Matthew-R59995 wrote:quoted
Hi Kumar, Actually I do many trials about it. Vxwerks Bootrom is smaller than U-Boot. The key difference between Bootrom and U-boot is that some source code of Bootrom is invisible to the users. Actually the rfi instruction which I point out is the first rfi instruction of Linux PowerPC bringup. Before that, it's TLB entry invalidation and temp TLB entry mapping. I check MMU setting carefully before coming Linux Kernel. I just want to know if other guys met similar scenario like me. I don't need the precise answer, just overall suggestion about it because I understand that not everyone has the same bootloader of mine, that bootloader is actually a customized bootloader.I understand that, thus I was asking what exact problem you were seeing to try and help.quoted
Anyway thank you. R9 point to LR register, mask the high 20 bit of r9 and send to r7, and then add 24, which means stride 6 instructions for rfi instruction execution. Of course, rfi can switch the TLB entry, both the previous TLB entry and the temp TLB entry point to the same physical address. I've checked it.I know what the code does, I wrote it :) - kumar _______________________________________________ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded ________________________________ Here's a new way to find what you're looking for - Yahoo! Answers _______________________________________________ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
-- /* * Steve Iribarne * Software Engineer * (aka Grunt) */