Joakim Tjernlund wrote:

In my typical example I need to invalidate a buffer before I give it to
the
CPM to be used as a receive buffer. Once given to the CPM there must be
no more writes to that buffer memory. When the CPM has received data
and written the data into the buffer and hands it over to the CPU
(usally via an interrupt) the next read from the CPU must access it from
the memory.  Does the above require a sync?

Probably not, I don't know much about the CPM though (and I assume this
is a system without any extra cpu's).

Does it take some time before a invalidate is completed?

Depends on your cpu; I don't know the details for your cpu.  Check your
manuals :)


Segher


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