Re: Latest OpenPic changes

On Fri, 11 Feb 2000, Benjamin Herrenschmidt wrote:

On Fri, Feb 11, 2000, Geert Uytterhoeven [off-list ref] wrote:

quoted

and OPENPIC_MASK is still set when the loop times out on enabling
IRQ_8259_CASCADE in chrp_init_IRQ(). How is this possible? There's an eieio()
after each register write and the mb() does sync.

Is this the only interrupt causing this behaviour ? I beleive that means
either the mask register is not implemented for the cascade or a hw bug.
I'll try to have a look at my docs this week-end.

Yes it is. It works fine for all other interrupts (MESH, sym53c8xx).

Gr{oetje,eeting}s,
--
Geert Uytterhoeven -- Linux/{m68k~Amiga,PPC~CHRP} -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds


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