On Wednesday 22 September 2021 14:03:25 David Laight wrote:

From: Jonas Dreßler

quoted

Sent: 14 September 2021 12:48

On the 88W8897 card it's very important the TX ring write pointer is
updated correctly to its new value before setting the TX ready
interrupt, otherwise the firmware appears to crash (probably because
it's trying to DMA-read from the wrong place). The issue is present in
the latest firmware version 15.68.19.p21 of the pcie+usb card.

Since PCI uses "posted writes" when writing to a register, it's not
guaranteed that a write will happen immediately. That means the pointer
might be outdated when setting the TX ready interrupt, leading to
firmware crashes especially when ASPM L1 and L1 substates are enabled
(because of the higher link latency, the write will probably take
longer).

So fix those firmware crashes by always using a non-posted write for
this specific register write. We do that by simply reading back the
register after writing it, just as a few other PCI drivers do.

This fixes a bug where during rx/tx traffic and with ASPM L1 substates
enabled (the enabled substates are platform dependent), the firmware
crashes and eventually a command timeout appears in the logs.

I think you need to change your terminology.
PCIe does have some non-posted write transactions - but I can't
remember when they are used.

In PCIe are all memory write requests as posted.

Non-posted writes in PCIe are used only for IO and config requests. But
this is not case for proposed patch change as it access only card's
memory space.

Technically this patch does not use non-posted memory write (as PCIe
does not support / provide it), just adds something like a barrier and
I'm not sure if it is really correct (you already wrote more details
about it, so I will let it be).

I'm not sure what is the correct terminology, I do not know how this
kind of write-followed-by-read "trick" is correctly called.