[RFC/RFT v2 04/12] ath9k: use common PCIe ASPM definces instead of custom ones

@@ -1028,10 +1028,6 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
 
-#define ATH_PCIE_CAP_LINK_CTRL	0x70
-#define ATH_PCIE_CAP_LINK_L0S	1
-#define ATH_PCIE_CAP_LINK_L1	2
-
 #define ATH9K_CLOCK_RATE_CCK		22
 #define ATH9K_CLOCK_RATE_5GHZ_OFDM	40
 #define ATH9K_CLOCK_RATE_2GHZ_OFDM	44

@@ -16,6 +16,7 @@
 
 #include <linux/nl80211.h>
 #include <linux/pci.h>
+#include <linux/pci-aspm.h>
 #include <linux/ath9k_platform.h>
 #include "ath9k.h"
 

@@ -94,14 +95,16 @@ static void ath_pci_bt_coex_prep(struct ath_common *common)
 {
 	struct ath_softc *sc = (struct ath_softc *) common->priv;
 	struct pci_dev *pdev = to_pci_dev(sc->dev);
+	int pos;
 	u8 aspm;
 
-	if (!pci_is_pcie(pdev))
+	pos = pci_pcie_cap(pdev);
+	if (!pos)
 		return;
 
-	pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
-	aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
-	pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
+	pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm);
+	aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
+	pci_write_config_byte(pdev, pos +  PCI_EXP_LNKCTL, aspm);
 }
 
 static void ath_pci_extn_synch_enable(struct ath_common *common)

@@ -128,6 +131,7 @@ static void ath_pci_check_aspm(struct ath_softc *sc)
 	struct ath_hw *ah = sc->sc_ah;
 	struct pci_dev *pdev = to_pci_dev(sc->dev);
 	struct pci_dev *parent;
+	int ppos;
 	u8 aspm;
 
 	ah->aspm_enabled = false;

@@ -139,8 +143,9 @@ static void ath_pci_check_aspm(struct ath_softc *sc)
 	if (WARN_ON(!parent))
 		return;
 
-	pci_read_config_byte(parent, ATH_PCIE_CAP_LINK_CTRL, &aspm);
-	if (aspm & (ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1))
+	ppos = pci_pcie_cap(parent);
+	pci_read_config_byte(parent, ppos +  PCI_EXP_LNKCTL, &aspm);
+	if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1))
 		ah->aspm_enabled = true;
 }