Thread (28 messages) 28 messages, 3 authors, 2021-02-11

Re: [PATCH v6 02/15] clk: tegra: Don't enable PLLE HW sequencer at init

From: Stephen Boyd <sboyd@kernel.org>
Date: 2021-02-11 03:07:19
Also in: linux-devicetree, linux-tegra, lkml

Quoting JC Kuo (2021-01-19 00:55:33)
PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-by: Thierry Reding <redacted>
---
Acked-by: Stephen Boyd <sboyd@kernel.org>
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