RE: [PATCH 07/16] dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions

Hi Geert-san,

Thank you for your review!

From: Geert Uytterhoeven, Sent: Friday, November 19, 2021 3:53 AM

Hi Shimoda-san,

On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda
[off-list ref] wrote:

quoted

Add all Clock Pulse Generator Core Clock Outputs for the Renesas
R-Car S4-8 (R8A779F0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for your patch!

quoted

--- /dev/null
+++ b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h

@@ -0,0 +1,65 @@

<snip>

quoted

+#define R8A779F0_CLK_SDSRC             35

I think we can leave out SDSRC, like on the other SoCs, as it's an
internal clock.

I got it. I'll fix it in v2.

Best regards,
Yoshihiro Shimoda