[PATCH 5/8] arm64: dts: s32g2: add serial/uart support
From: Chester Lin <hidden>
Date: 2021-08-05 06:55:54
Also in:
linux-arm-kernel, linux-devicetree, lkml
Subsystem:
arm/freescale imx / mxc arm architecture, arm/nxp s32g architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
Add serial/uart support for NXP S32G2. Signed-off-by: Chester Lin <redacted> --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 31 ++++++++++++++++++++++++ 1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 3321819c1a2d..0076eacad8a6 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi@@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (c) 2021 SUSE LLC + * Copyright 2017-2020 NXP */ #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -11,6 +12,12 @@ / { #address-cells = <2>; #size-cells = <2>; + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + cpus { #address-cells = <1>; #size-cells = <0>;
@@ -82,6 +89,30 @@ soc { ranges; + uart0: serial@401c8000 { + compatible = "fsl,s32g2-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0 0x401c8000 0 0x3000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + uart1: serial@401cc000 { + compatible = "fsl,s32g2-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0 0x401cc000 0 0x3000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + uart2: serial@402bc000 { + compatible = "fsl,s32g2-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0 0x402bc000 0 0x3000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + gic: interrupt-controller@50800000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>;
--
2.30.0