On Tue, Feb 28, 2012 at 06:46:12PM +0900, Chanho Min wrote:

quoted

Because the flags are manipulated to give the illusion of a one byte
FIFO, as stated in the TRM.

Yes. It is the problem that rx interrupt is pended with this status as
I mentioned.

Which is why my patch explicitly clears the receive interrupt status
before requesting the interrupt.  Have you read my patch?
 

quoted

And we don't set the mask register to 1 until later.

In the last part of startup, set to 1. Interrupt can be occurred just
after it.

uap->im = UART011_RTIM;
if (!pl011_dma_rx_running(uap))
 uap->im |= UART011_RXIM;
 writew(uap->im, uap->port.membase + UART011_IMSC);

quoted

But we want to do the transmit interrupt provocation with the FIFO disabled.

I know. It's test only.

Wrong, it's fundamental to the UARTs operation.