Re: [PATCH 01/13] dt-bindings: interrupt-controller: create a header for RISC-V interrupts
From: Heiko Stübner <heiko@sntech.de>
Date: 2021-11-23 11:08:17
Also in:
linux-crypto, linux-devicetree, linux-gpio, linux-i2c, linux-riscv, linux-spi, linux-usb, lkml
Am Montag, 8. November 2021, 16:05:42 CET schrieb conor.dooley@microchip.com:
quoted hunk ↗ jump to hunk
From: Ivan Griffin <redacted> Provide named identifiers for device tree for RISC-V interrupts. Licensed under GPL and MIT, as this file may be useful to any OS that uses device tree. Signed-off-by: Ivan Griffin <redacted> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- .../interrupt-controller/riscv-hart.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.hdiff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h new file mode 100644 index 000000000000..e1c32f6090ac --- /dev/null +++ b/include/dt-bindings/interrupt-controller/riscv-hart.h@@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2021 Microchip Technology Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H + +#define HART_INT_U_SOFT 0 +#define HART_INT_S_SOFT 1 +#define HART_INT_M_SOFT 3 +#define HART_INT_U_TIMER 4 +#define HART_INT_S_TIMER 5 +#define HART_INT_M_TIMER 7 +#define HART_INT_U_EXT 8 +#define HART_INT_S_EXT 9 +#define HART_INT_M_EXT 11
(1) From checking clic doc [0] I see an additional 12 CLIC software interrupt defined. (2) The doc states that the ordering is a recommendation and "not mandatory in all incarnations of the CLIC" Is that clarified somewhere else that this more than recommended? Thanks Heiko [0] https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc
+ +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */