Kar Hin Ong [off-list ref] writes:

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From Intel Xeon Processor E5/E7 v3 Product Family External Design
Specification (EDS), Volume One: Architecture, section 13.1 (Legacy
PCI Interrupt Handling), it mention: "If the I/OxAPIC entry is
masked (via the 'mask' bit in the corresponding Redirection Table
Entry), then the corresponding PCI Express interrupt(s) is forwarded
to the legacy PCH"

Oh well. Really useful behaviour - NOT!

Second thoughts on this. This behaviour is intentional to make PCI
interrupts work even when the IOAPIC is not initialized at all.

I don't have access to the document you mentioned, but I know that
chipsets have a knob to control that behaviour. Just checked a few
chipset docs and they contain the same sentence, but then in the next
paragraph they say:

 "If the I/OxAPIC entry is masked (via the mask bit in the corresponding
  Redirection Table Entry), then the corresponding PCI Express
  interrupt(s) is forwarded to the legacy ICH, provided the Disable PCI
  INTx Routing to ICH bit is clear, Section 19.10.2.27, QPIPINTRC: Intel
  QuickPath Interconnect Protocol Interrupt Control."

That control bit is 0 after reset, so the legacy forwarding works.

Another way to avoid this is to use MSI interrupts instead of the legacy
PCI ones, which is recommended for various reasons (including
performance) anyway.

Can you please provide the exact CPU and PCH types and the output of
'lspci -vvv'?

Thanks,

        tglx