Re: [PATCH 01/19] x86/cpufreatures: add AMD CPPC extension feature flag

Hi Boris,

On Fri, Sep 10, 2021 at 01:58:19AM +0800, Borislav Petkov wrote:

On Wed, Sep 08, 2021 at 10:59:43PM +0800, Huang Rui wrote:

quoted

Add Collaborative Processor Performance Control Extension feature flag
for AMD processors.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index d0ce5cfd3ac1..f7aea50e3371 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h

@@ -313,6 +313,7 @@
 #define X86_FEATURE_AMD_SSBD		(13*32+24) /* "" Speculative Store Bypass Disable */
 #define X86_FEATURE_VIRT_SSBD		(13*32+25) /* Virtualized Speculative Store Bypass Disable */
 #define X86_FEATURE_AMD_SSB_NO		(13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
+#define X86_FEATURE_AMD_CPPC_EXT	(13*32+27) /* Collaborative Processor Performance Control Extension */

Why not simply X86_FEATURE_AMD_CPPC ?

This feature flag indicates the full MSR hardware solution of AMD P-States,
if it is not set, that means we will go with in shared memory hardware
solution. So we name this as extension. I will explain the details in the
commit log at V2. ;-)

Thanks,
Ray