On Sun, Jan 26, 2025 at 01:39:05PM +0200, Dmitry Baryshkov wrote:

On Sun, Jan 26, 2025 at 12:59:52PM +0530, Manivannan Sadhasivam wrote:

quoted

On January 25, 2025 11:00:23 PM GMT+05:30, Dmitry Baryshkov [off-list ref] wrote:

quoted

On Sat, Jan 25, 2025 at 04:31:19AM +0100, Konrad Dybcio wrote:

quoted

From: Konrad Dybcio <redacted>

Add a new, common configuration for Gen4x4 V6 PHYs without an init
sequence.

The bootloader configures the hardware once and the OS retains that
configuration by using the NOCSR reset line (which doesn't drop
register state on assert) in place of the "full reset" one.

I know your opinion, but my 2c would still be for not depending on the
bootloader. I think that was the rule for ages for many possible
reasons.

But if Linux or other OS can trust the bootloader, then it makes perfect sense to rely on them. Obviously, the question here is that on which platforms this level of trust should be established. And the answer I got was starting from the compute platforms (atleast X1E).

Is there any way how those values can be lost that we still might want
to support ? The GDSC going to the OFF state? Some deep sleep state or a
power collapse? Actual suspend to RAM (instead of current S2Idle)?

As per Konrad's reply to my identical question, PHY register state is supposed
to be maintained by MX domain even during CX PC. This seem to be case on X1E
based platforms (compute).

quoted

So let's take it on an experimental basis and see how it goes? If at all any problem arises, we can always resort to in kernel sequences.

Sounds like a good proposal. Can possibly have a corresponding 'do not
merge' patch with actual init tables?

I don't find it really required. If the init sequences are really needed, we
know where to find them.

- Mani

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