Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache

Santosh Shilimkar had written, on 12/20/2010 07:29 AM, the following:
[..]

So may be you could update the change log something like below.

While coming out of MPU OSWR/OFF states, L2 controller is reseted.
The reset behavior is implementation specific as per ARMv7 TRM and
hence $L2 needs to be invalidated before it's use. Since the
AUXCTRL register is also reconfigured, disable L2 cache before
invalidating it and re-enables it afterwards. This is as per
Cortex-A8 ARM documentation.
Currently this is identified as being needed on OMAP3630 as the
disable/enable is done from "public side" while, on OMAP3430, this
is done in the "secure side".

Thanks, will update the rev5 patch with this commit log.

-- 
Regards,
Nishanth Menon