RE: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache

-----Original Message-----
From: Nishanth Menon [mailto:nm@ti.com]
Sent: Monday, December 20, 2010 5:15 PM
To: Santosh Shilimkar
Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony
Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while
invalidating L2 cache

Santosh Shilimkar wrote, on 12/20/2010 01:13 AM:
[..]

quoted

quoted

This is be done according to ARM documentation. Currently this is
identified
as being needed on OMAP3630 as the disable/enable is done from

"public

quoted

quoted

side"
while, on OMAP3430, this is done in the "secure side".

Can you point me to ARM doc which says " for L2 invalidation, the
controller
needs to be disabled" ?

please see section 8.3 of the Cortex-A8 TRM

Yes. Have seen it and it doesn't say at least what your patch
description is saying.