[AMD Public Use]

-----Original Message-----
From: Christoph Hellwig <hch@lst.de>
Sent: Tuesday, May 25, 2021 2:21 AM
To: Liang, Prike <redacted>
Cc: kbusch@kernel.org; axboe@fb.com; hch@lst.de; sagi@grimberg.me;
linux-nvme@lists.infradead.org; Deucher, Alexander
[off-list ref]; S-k, Shyam-sundar <Shyam-sundar.S-
k@amd.com>; Limonciello, Mario [off-list ref]
Subject: Re: [PATCH] nvme-pci: set some AMD PCIe downstream storage
device to D3 for s2idle

On Tue, May 25, 2021 at 10:48:59AM +0800, Prike Liang wrote:

quoted

+#ifdef CONFIG_X86
+#include <asm/cpu_device_id.h>
+#endif

 #include "trace.h"
 #include "nvme.h"

@@ -2828,6 +2831,16 @@ static unsigned long

check_vendor_combination_bug(struct pci_dev *pdev)  }

 #ifdef CONFIG_ACPI
+
+#ifdef CONFIG_X86
+static const struct x86_cpu_id storage_d3_cpu_ids[] = {
+	X86_MATCH_VENDOR_FAM_MODEL(AMD, 25, 80, NULL),

/*Cezanne*/

quoted

+	X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 96, NULL),

/*Renoir*/

quoted

+	X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 104,

NULL),/*Lucienne*/

quoted

+	{}
+};
+#endif

This is completely unacceptable.  The NVMe driver could not care less what
CPU we on.  We need information from the PCI or power managment core
on how broken the power management of the root port is, not this kind of
crap in a low-level driver, with potentially many more needing the same kind
of quirk in the future.

Hans,

Any ideas on how to handle this at that platform level?  We need to select the NVME_QUIRK_SIMPLE_SUSPEND flag on certain AMD platforms.  This is a platform firmware requirement.  It's not an NVME specific requirement, it's not a PCIe specific requirement, it's a platform specific requirement.  DMI matching doesn't really make sense because it affects all AMD platforms of a certain generation.

Thanks,

Alex

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