From: Jason Gunthorpe <jgg@ziepe.ca>
Sent: Tuesday, February 2, 2021 7:44 AM

On Fri, Jan 29, 2021 at 10:09:03AM +0000, Tian, Kevin wrote:

quoted

quoted

SVA is not doom to work with IO page fault only. If we have SVA+pin,
we would get both sharing address and stable I/O latency.

Isn't it like a traditional MAP_DMA API (imply pinning) plus specifying
cpu_va of the memory pool as the iova?

I think their issue is the HW can't do the cpu_va trick without also
involving the system IOMMU in a SVA mode

This is the part that I didn't understand. Using cpu_va in a MAP_DMA
interface doesn't require device support. It's just an user-specified
address to be mapped into the IOMMU page table. On the other hand,
sharing CPU page table through a SVA interface for an usage where I/O 
page faults must be completely avoided seems a misleading attempt. 
Even if people do want this model (e.g. mix pinning+fault), it should be
a mm syscall as Greg pointed out, not specific to sva.

Thanks
Kevin