Hi Florian,

I love your patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v5.12-rc4 next-20210326]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Florian-Fainelli/MIPS-Add-support-for-CONFIG_DEBUG_VIRTUAL/20210327-061711
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 0f4498cef9f5cd18d7c6639a2a902ec1edc5be4e
config: mips-randconfig-s032-20210326 (attached as .config)
compiler: mipsel-linux-gcc (GCC) 9.3.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # apt-get install sparse
        # sparse version: v0.6.3-277-gc089cd2d-dirty
        # https://github.com/0day-ci/linux/commit/ee0c68ff98559388eac4d40c8f8724e21f7ba5f6
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Florian-Fainelli/MIPS-Add-support-for-CONFIG_DEBUG_VIRTUAL/20210327-061711
        git checkout ee0c68ff98559388eac4d40c8f8724e21f7ba5f6
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=mips 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <redacted>


sparse warnings: (new ones prefixed by >>)
   command-line: note: in included file:
   builtin:1:9: sparse: sparse: preprocessor token __ATOMIC_ACQUIRE redefined
   builtin:0:0: sparse: this was the original definition
   builtin:1:9: sparse: sparse: preprocessor token __ATOMIC_SEQ_CST redefined
   builtin:0:0: sparse: this was the original definition
   builtin:1:9: sparse: sparse: preprocessor token __ATOMIC_ACQ_REL redefined
   builtin:0:0: sparse: this was the original definition
   builtin:1:9: sparse: sparse: preprocessor token __ATOMIC_RELEASE redefined
   builtin:0:0: sparse: this was the original definition

quoted

arch/mips/kernel/vdso.c:161:41: sparse: sparse: cast removes address space '__iomem' of expression

vim +/__iomem +161 arch/mips/kernel/vdso.c

    88	
    89	int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
    90	{
    91		struct mips_vdso_image *image = current->thread.abi->vdso;
    92		struct mm_struct *mm = current->mm;
    93		unsigned long gic_size, vvar_size, size, base, data_addr, vdso_addr, gic_pfn;
    94		struct vm_area_struct *vma;
    95		int ret;
    96	
    97		if (mmap_write_lock_killable(mm))
    98			return -EINTR;
    99	
   100		if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT)) {
   101			/* Map delay slot emulation page */
   102			base = mmap_region(NULL, STACK_TOP, PAGE_SIZE,
   103					VM_READ | VM_EXEC |
   104					VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC,
   105					0, NULL);
   106			if (IS_ERR_VALUE(base)) {
   107				ret = base;
   108				goto out;
   109			}
   110		}
   111	
   112		/*
   113		 * Determine total area size. This includes the VDSO data itself, the
   114		 * data page, and the GIC user page if present. Always create a mapping
   115		 * for the GIC user area if the GIC is present regardless of whether it
   116		 * is the current clocksource, in case it comes into use later on. We
   117		 * only map a page even though the total area is 64K, as we only need
   118		 * the counter registers at the start.
   119		 */
   120		gic_size = mips_gic_present() ? PAGE_SIZE : 0;
   121		vvar_size = gic_size + PAGE_SIZE;
   122		size = vvar_size + image->size;
   123	
   124		/*
   125		 * Find a region that's large enough for us to perform the
   126		 * colour-matching alignment below.
   127		 */
   128		if (cpu_has_dc_aliases)
   129			size += shm_align_mask + 1;
   130	
   131		base = get_unmapped_area(NULL, vdso_base(), size, 0, 0);
   132		if (IS_ERR_VALUE(base)) {
   133			ret = base;
   134			goto out;
   135		}
   136	
   137		/*
   138		 * If we suffer from dcache aliasing, ensure that the VDSO data page
   139		 * mapping is coloured the same as the kernel's mapping of that memory.
   140		 * This ensures that when the kernel updates the VDSO data userland
   141		 * will observe it without requiring cache invalidations.
   142		 */
   143		if (cpu_has_dc_aliases) {
   144			base = __ALIGN_MASK(base, shm_align_mask);
   145			base += ((unsigned long)vdso_data - gic_size) & shm_align_mask;
   146		}
   147	
   148		data_addr = base + gic_size;
   149		vdso_addr = data_addr + PAGE_SIZE;
   150	
   151		vma = _install_special_mapping(mm, base, vvar_size,
   152					       VM_READ | VM_MAYREAD,
   153					       &vdso_vvar_mapping);
   154		if (IS_ERR(vma)) {
   155			ret = PTR_ERR(vma);
   156			goto out;
   157		}
   158	
   159		/* Map GIC user page. */
   160		if (gic_size) {
 > 161			gic_pfn = virt_to_phys((void *)mips_gic_base + MIPS_GIC_USER_OFS) >> PAGE_SHIFT;

---
0-DAY CI Kernel Test Service, Intel Corporation
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