Re: [PATCH] MIPS: clean up CONFIG_MIPS_PGD_C0_CONTEXT handling
From: "Maciej W. Rozycki" <macro@orcam.me.uk>
Date: 2021-02-28 23:00:33
Also in:
linux-arch, linux-mm
On Sat, 27 Feb 2021, Huang Pei wrote:
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index 2000bb2b0220..517509ad8596 100644--- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig@@ -2142,6 +2142,7 @@ config CPU_SUPPORTS_HUGEPAGES depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA)) config MIPS_PGD_C0_CONTEXT bool + depends on 64BIT default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
I guess you want: default y if (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP at the same time too. Otherwise you have cruft left behind.
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diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index a7521b8f7658..5bb9724578f7 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c@@ -1106,6 +1106,7 @@ struct mips_huge_tlb_info { bool need_reload_pte; }; +#ifdef CONFIG_64BIT static struct mips_huge_tlb_info build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, struct uasm_reloc **r, unsigned int tmp,
Does it actually build without a warning for !CONFIG_64BIT given the reference below?
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@@ -1164,8 +1165,8 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, if (pgd_reg == -1) { vmalloc_branch_delay_filled = 1; - /* 1 0 1 0 1 << 6 xkphys cached */ - uasm_i_ori(p, ptr, ptr, 0x540); + /* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */ + uasm_i_ori(p, ptr, ptr, (CAC_BASE >> 53));
Instead I'd paper the issue over by casting the constant to `s64'. Or better yet fixed it properly by defining CAC_BASE, etc. as `unsigned long long' long rather than `unsigned long' to stop all this nonsense (e.g. PHYS_TO_XKPHYS already casts the result to `s64'). Thomas, WDYT? Maciej