Re: [PATCH] MIPS: loongson64: use 0b011 instead of 0b101 as xphys cached
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2021-02-20 05:32:35
Also in:
linux-arch, linux-mm
在 2021/2/20 上午11:31, Huang Pei 写道:
quoted hunk
Loongson 3 use *0b011* as Cachable(not 0b101), this only affect loongson64 without enough CP0 Kscratch for holding current pgd. 3A2000+ use CP0 PWbase holding current (user) pgd Signed-off-by: Huang Pei <redacted> --- arch/mips/mm/tlbex.c | 7 +++++++ 1 file changed, 7 insertions(+)diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index a7521b8f7658..51effa5dbf9d 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c@@ -848,8 +848,15 @@ void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, /* Clear lower 23 bits of context. */ uasm_i_dins(p, ptr, 0, 0, 23); +#ifdef CONFIG_CPU_LOONGSON64 + /* 1 0 0 1 1 << 6 xkphys cached */ + /* 0x98xx xxxx xxxx xxxx */ + uasm_i_ori(p, ptr, ptr, 0x4c0);
Hi Pei, What about (CAC_BASE >> 53) instead of magic number? Also there is another similar usage at build_fast_tlb_refill_handler, please fix it as well. Thanks. - Jiaxun
quoted hunk
+#else /* 1 0 1 0 1 << 6 xkphys cached */ + /* 0xa8xx xxxx xxxx xxxx */ uasm_i_ori(p, ptr, ptr, 0x540); +#endif uasm_i_drotr(p, ptr, ptr, 11); #elif defined(CONFIG_SMP) UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);