Re: [PATCH] MIPS: Support binutils configured with --enable-mips-fix-loongson3-llsc=yes
From: Maciej W. Rozycki <hidden>
Date: 2021-01-09 20:03:06
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lkml, stable
On Sat, 9 Jan 2021, Aurelien Jarno wrote:
quoted hunk ↗ jump to hunk
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index cd4343edeb11..5ffdd67093bc 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile@@ -136,6 +136,25 @@ cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \ # cflags-y += -fno-stack-check +# binutils from v2.35 when built with --enable-mips-fix-loongson3-llsc=yes, +# supports an -mfix-loongson3-llsc flag which emits a sync prior to each ll +# instruction to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h +# for a description). +# +# We disable this in order to prevent the assembler meddling with the +# instruction that labels refer to, ie. if we label an ll instruction: +# +# 1: ll v0, 0(a0) +# +# ...then with the assembler fix applied the label may actually point at a sync +# instruction inserted by the assembler, and if we were using the label in an +# exception table the table would no longer contain the address of the ll +# instruction.
Interesting. Given that a MIPS assembler is generally free to shuffle instructions as it sees fit in its default reorder mode as long as that does not change the semantics of the code executed, shouldn't we instead place all label/instruction pairs used for exception handling in noreorder blocks so as to make sure the label refers to the instruction an exception handler expects it to? E.g. for the case quoted above: .set push .set noreorder 1: ll v0, 0(a0) .set pop Maciej