[PATCH 10/11] MIPS: Octeon: Make register functions node aware.
From: Steven J. Hill <hidden>
Date: 2017-09-15 17:37:59
Subsystem:
mips, the rest · Maintainers:
Thomas Bogendoerfer, Linus Torvalds
From: "Steven J. Hill" <redacted> Signed-off-by: Steven J. Hill <redacted> Acked-by: David Daney <redacted> --- arch/mips/include/asm/octeon/cvmx.h | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index d1d1935..1c0a929 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h@@ -272,6 +272,20 @@ static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val) if (((csr_addr >> 40) & 0x7ffff) == (0x118)) cvmx_read64(CVMX_MIO_BOOT_BIST_STAT); } +static inline void cvmx_write_csr_node(uint64_t node, uint64_t csr_addr, + uint64_t val) +{ + uint64_t node_addr; + uint64_t composite_csr_addr; + node_addr = (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT; + + composite_csr_addr = (csr_addr & ~CVMX_NODE_IO_MASK) | node_addr; + + cvmx_write64_uint64(composite_csr_addr, val); + if (((csr_addr >> 40) & 0x7ffff) == (0x118)) { + cvmx_read64_uint64(CVMX_MIO_BOOT_BIST_STAT | node_addr); + } +} static inline void cvmx_writeq_csr(void __iomem *csr_addr, uint64_t val) {
@@ -295,6 +309,14 @@ static inline uint64_t cvmx_readq_csr(void __iomem *csr_addr) return cvmx_read_csr((__force uint64_t) csr_addr); } +static inline uint64_t cvmx_read_csr_node(uint64_t node, uint64_t csr_addr) +{ + uint64_t node_addr; + + node_addr = (csr_addr & ~CVMX_NODE_IO_MASK) | (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT; + return cvmx_read_csr(node_addr); +} + static inline void cvmx_send_single(uint64_t data) { const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
@@ -421,7 +443,7 @@ static inline uint64_t cvmx_get_cycle_global(void) * 2) Check if ("type".s."field" "op" "value") * 3) If #2 isn't true loop to #1 unless too much time has passed. */ -#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\ +#define CVMX_WAIT_FOR_FIELD64_NODE(node, address, type, field, op, value, timeout_usec) \ ( \ { \ int result; \
@@ -430,7 +452,7 @@ static inline uint64_t cvmx_get_cycle_global(void) cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \ type c; \ while (1) { \ - c.u64 = cvmx_read_csr(address); \ + c.u64 = cvmx_read_csr_node(node, address); \ if ((c.s.field) op(value)) { \ result = 0; \ break; \
@@ -446,6 +468,9 @@ static inline uint64_t cvmx_get_cycle_global(void) /***************************************************************************/ +#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec) \ + CVMX_WAIT_FOR_FIELD64_NODE(0, address, type, field, op, value, timeout_usec) + /* Return the number of cores available in the chip */ static inline uint32_t cvmx_octeon_num_cores(void) {
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2.1.4