[PATCH RESEND V2 4/7] MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6
From: Huacai Chen <hidden>
Date: 2017-03-16 13:04:08
Also in:
stable
Subsystem:
mips, the rest · Maintainers:
Thomas Bogendoerfer, Linus Torvalds
Some newer Loongson-3 has 64 bytes cache line size, so we select MIPS_L1_CACHE_SHIFT_6. Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen <redacted> --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e0bb576..c3c7d8a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig@@ -1373,6 +1373,7 @@ config CPU_LOONGSON3 select WEAK_ORDERING select WEAK_REORDERING_BEYOND_LLSC select MIPS_PGD_C0_CONTEXT + select MIPS_L1_CACHE_SHIFT_6 select GPIOLIB help The Loongson 3 processor implements the MIPS64R2 instruction
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2.7.0