Re: [PATCH] MIPS: Lantiq: Fix cascaded IRQ setup
From: James Hogan <hidden>
Date: 2017-02-13 11:12:24
On Sun, Feb 12, 2017 at 12:05:08PM +0100, Felix Fietkau wrote:
On 2017-02-12 00:50, Hauke Mehrtens wrote:quoted
On 02/12/2017 12:19 AM, James Hogan wrote:quoted
On Thu, Jan 19, 2017 at 12:28:22PM +0100, Felix Fietkau wrote:quoted
With the IRQ stack changes integrated, the XRX200 devices started emitting a constant stream of kernel messages like this: [ 565.415310] Spurious IRQ: CAUSE=0x1100c300 This appears to be caused by IP0 firing for some reason without being handled. Fix this by setting up IP2-6 as a proper chained IRQ handler and calling do_IRQ for all MIPS CPU interrupts. Cc: john@phrozen.org Cc: stable@vger.kernel.org Signed-off-by: Felix Fietkau <nbd@nbd.name>Is this still applicable after Matt's fix is applied? https://patchwork.linux-mips.org/patch/15110/
quoted
I just tried it without Matt's and Felix's fix and I saw the problem, then I applied Matt's fix and the problem was gone.I still think it should be applied, since it replaces some hacks with cleaner code.
Okay, I'll drop cc stable (since cpu_has_vint is hardwired to 1 on lantiq platform), and change the last paragraph of the commit message to say:
This is caused by IP0 getting handled by plat_irq_dispatch() rather than
its vectored interrupt handler, which is fixed by commit de856416e714
("MIPS: IRQ Stack: Fix erroneous jal to plat_irq_dispatch").
Fix plat_irq_dispatch() to handle non-vectored IPI interrupts correctly
by setting up IP2-6 as proper chained IRQ handlers and calling do_IRQ
for all MIPS CPU interrupts.I think thats accurate, but let me know if you want it changed. Thanks James
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