Re: [PATCH 2/4] MIPS: BMIPS: Add support GPIO device nodes
From: Jaedon Shin <hidden>
Date: 2016-08-09 01:44:14
Also in:
linux-devicetree
Hi Jonas, On Aug 8, 2016, at 11:06 PM, Jonas Gorski [off-list ref] wrote:
Hi, please always include devicetree for any dts(i) related changes. On 8 August 2016 at 04:17, Jaedon Shin [off-list ref] wrote:quoted
Adds GPIO device nodes to BCM7xxx MIPS based SoCs. Signed-off-by: Jaedon Shin <redacted> --- arch/mips/boot/dts/brcm/bcm7125.dtsi | 12 ++++++++++ arch/mips/boot/dts/brcm/bcm7346.dtsi | 37 +++++++++++++++++++++++++++++++ arch/mips/boot/dts/brcm/bcm7358.dtsi | 37 +++++++++++++++++++++++++++++++ arch/mips/boot/dts/brcm/bcm7360.dtsi | 37 +++++++++++++++++++++++++++++++ arch/mips/boot/dts/brcm/bcm7362.dtsi | 37 +++++++++++++++++++++++++++++++ arch/mips/boot/dts/brcm/bcm7420.dtsi | 12 ++++++++++ arch/mips/boot/dts/brcm/bcm7425.dtsi | 37 +++++++++++++++++++++++++++++++ arch/mips/boot/dts/brcm/bcm7435.dtsi | 37 +++++++++++++++++++++++++++++++ arch/mips/boot/dts/brcm/bcm97125cbmb.dts | 4 ++++ arch/mips/boot/dts/brcm/bcm97346dbsmb.dts | 8 +++++++ arch/mips/boot/dts/brcm/bcm97358svmb.dts | 8 +++++++ arch/mips/boot/dts/brcm/bcm97360svmb.dts | 8 +++++++ arch/mips/boot/dts/brcm/bcm97362svmb.dts | 8 +++++++ arch/mips/boot/dts/brcm/bcm97420c.dts | 4 ++++ arch/mips/boot/dts/brcm/bcm97425svmb.dts | 8 +++++++ arch/mips/boot/dts/brcm/bcm97435svmb.dts | 8 +++++++ 16 files changed, 302 insertions(+)diff --git a/arch/mips/boot/dts/brcm/bcm7125.dtsi b/arch/mips/boot/dts/brcm/bcm7125.dtsi index 97191f6bca28..746ed06c85de 100644 --- a/arch/mips/boot/dts/brcm/bcm7125.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7125.dtsi@@ -197,6 +197,18 @@ status = "disabled"; }; + upg_gio: gpio@406700 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406700 0x80>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 18>; + }; + ehci0: usb@488300 { compatible = "brcm,bcm7125-ehci", "generic-ehci"; reg = <0x488300 0x100>;diff --git a/arch/mips/boot/dts/brcm/bcm7346.dtsi b/arch/mips/boot/dts/brcm/bcm7346.dtsi index eb7b19a32e3e..1ef7540238be 100644 --- a/arch/mips/boot/dts/brcm/bcm7346.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7346.dtsi@@ -232,6 +232,43 @@ status = "disabled"; }; + aon_pm_l2_intc: aon_pm_l2_intc@408440 {interrupt-controller@quoted
+ compatible = "brcm,l2-intc"; + reg = <0x408440 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <52>; + brcm,irq-can-wake; + }; + + upg_gio: gpio@406700 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406700 0x60>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 16>; + }; + + upg_gio_aon: gpio@408c00 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x408c00 0x60>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_aon_irq0_intc>; + interrupts = <6>; + interrupts-extended = <&upg_aon_irq0_intc 6>, + <&aon_pm_l2_intc 5>; + wakeup-source; + brcm,gpio-bank-widths = <27 32 2>; + }; + enet0: ethernet@430000 { phy-mode = "internal"; phy-handle = <&phy1>;diff --git a/arch/mips/boot/dts/brcm/bcm7358.dtsi b/arch/mips/boot/dts/brcm/bcm7358.dtsi index b2276b1e12d4..bb099ee046a1 100644 --- a/arch/mips/boot/dts/brcm/bcm7358.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7358.dtsi@@ -216,6 +216,43 @@ status = "disabled"; }; + aon_pm_l2_intc: aon_pm_l2_intc@408240 {interrupt-controller@quoted
+ compatible = "brcm,l2-intc"; + reg = <0x408240 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <49>; + brcm,irq-can-wake; + }; + + upg_gio: gpio@406500 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406500 0xa0>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 29 4>; + }; + + upg_gio_aon: gpio@408c00 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x408c00 0x60>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_aon_irq0_intc>; + interrupts = <6>; + interrupts-extended = <&upg_aon_irq0_intc 6>, + <&aon_pm_l2_intc 5>; + wakeup-source; + brcm,gpio-bank-widths = <21 32 2>; + }; + enet0: ethernet@430000 { phy-mode = "internal"; phy-handle = <&phy1>;diff --git a/arch/mips/boot/dts/brcm/bcm7360.dtsi b/arch/mips/boot/dts/brcm/bcm7360.dtsi index e414af1e14ff..0aeb3de7fbc2 100644 --- a/arch/mips/boot/dts/brcm/bcm7360.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7360.dtsi@@ -208,6 +208,43 @@ status = "disabled"; }; + aon_pm_l2_intc: aon_pm_l2_intc@408440 {interrupt-controller@quoted
+ compatible = "brcm,l2-intc"; + reg = <0x408440 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <49>; + brcm,irq-can-wake; + }; + + upg_gio: gpio@406500 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406500 0xa0>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 29 4>; + }; + + upg_gio_aon: gpio@408c00 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x408c00 0x60>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_aon_irq0_intc>; + interrupts = <6>; + interrupts-extended = <&upg_aon_irq0_intc 6>, + <&aon_pm_l2_intc 5>; + wakeup-source; + brcm,gpio-bank-widths = <21 32 2>; + }; + enet0: ethernet@430000 { phy-mode = "internal"; phy-handle = <&phy1>;diff --git a/arch/mips/boot/dts/brcm/bcm7362.dtsi b/arch/mips/boot/dts/brcm/bcm7362.dtsi index 3bd1c0111d43..9a1f6ffc343d 100644 --- a/arch/mips/boot/dts/brcm/bcm7362.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7362.dtsi@@ -204,6 +204,43 @@ status = "disabled"; }; + aon_pm_l2_intc: aon_pm_l2_intc@408440 {interrupt-controller@quoted
+ compatible = "brcm,l2-intc"; + reg = <0x408440 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <49>; + brcm,irq-can-wake; + }; + + upg_gio: gpio@406500 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406500 0xa0>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 29 4>; + }; + + upg_gio_aon: gpio@408c00 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x408c00 0x60>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_aon_irq0_intc>; + interrupts = <6>; + interrupts-extended = <&upg_aon_irq0_intc 6>, + <&aon_pm_l2_intc 5>; + wakeup-source; + brcm,gpio-bank-widths = <21 32 2>; + }; + enet0: ethernet@430000 { phy-mode = "internal"; phy-handle = <&phy1>;diff --git a/arch/mips/boot/dts/brcm/bcm7420.dtsi b/arch/mips/boot/dts/brcm/bcm7420.dtsi index 27c3d45556b9..0d391d77c780 100644 --- a/arch/mips/boot/dts/brcm/bcm7420.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7420.dtsi@@ -213,6 +213,18 @@ status = "disabled"; }; + upg_gio: gpio@406700 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406700 0x80>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 27>; + }; + enet0: ethernet@468000 { phy-mode = "internal"; phy-handle = <&phy1>;diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi index 9ab65d64e948..04306a92b8eb 100644 --- a/arch/mips/boot/dts/brcm/bcm7425.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi@@ -231,6 +231,43 @@ status = "disabled"; }; + aon_pm_l2_intc: aon_pm_l2_intc@408440 {interrupt-controller@quoted
+ compatible = "brcm,l2-intc"; + reg = <0x408440 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <48>; + brcm,irq-can-wake; + }; + + upg_gio: gpio@406700 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406700 0x80>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 21>; + }; + + upg_gio_aon: gpio@4094c0 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x4094c0 0x40>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_aon_irq0_intc>; + interrupts = <6>; + interrupts-extended = <&upg_aon_irq0_intc 6>, + <&aon_pm_l2_intc 5>; + wakeup-source; + brcm,gpio-bank-widths = <18 4>; + }; + enet0: ethernet@b80000 { phy-mode = "internal"; phy-handle = <&phy1>;diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi index 7801169416e7..c4883643ab61 100644 --- a/arch/mips/boot/dts/brcm/bcm7435.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi@@ -246,6 +246,43 @@ status = "disabled"; }; + aon_pm_l2_intc: aon_pm_l2_intc@408440 {interrupt-controller@quoted
+ compatible = "brcm,l2-intc"; + reg = <0x408440 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <53>; + brcm,irq-can-wake; + }; + + upg_gio: gpio@406700 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406700 0x80>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 21>; + }; + + upg_gio_aon: gpio@4094c0 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x4094c0 0x40>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_aon_irq0_intc>; + interrupts = <6>; + interrupts-extended = <&upg_aon_irq0_intc 6>, + <&aon_pm_l2_intc 5>; + wakeup-source; + brcm,gpio-bank-widths = <18 4>; + }; + enet0: ethernet@b80000 { phy-mode = "internal"; phy-handle = <&phy1>;diff --git a/arch/mips/boot/dts/brcm/bcm97125cbmb.dts b/arch/mips/boot/dts/brcm/bcm97125cbmb.dts index 5c24eacd72dd..91590ff55d52 100644 --- a/arch/mips/boot/dts/brcm/bcm97125cbmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97125cbmb.dts@@ -49,6 +49,10 @@ status = "okay";}; +&upg_gio { + status = "okay"; +}; +You don't set its status in the dtsi, it will be enabled by default, and you can drop this change.quoted
/* FIXME: USB is wonky; disable it for now */ &ehci0 { status = "disabled";diff --git a/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts index 2c55ab094a29..e91a21f75a13 100644 --- a/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts@@ -57,6 +57,14 @@ status = "okay";}; +&upg_gio { + status = "okay"; +}; + +&upg_gio_aon { + status = "okay"; +}; +You don't set their status in the dtsi, they will be enabled by default, and you can drop this change.quoted
&enet0 { status = "okay"; };diff --git a/arch/mips/boot/dts/brcm/bcm97358svmb.dts b/arch/mips/boot/dts/brcm/bcm97358svmb.dts index 757fe9d5f4df..d475a152eb2a 100644 --- a/arch/mips/boot/dts/brcm/bcm97358svmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97358svmb.dts@@ -53,6 +53,14 @@ status = "okay";}; +&upg_gio { + status = "okay"; +}; + +&upg_gio_aon { + status = "okay"; +}; +You don't set their status in the dtsi, they will be enabled by default, and you can drop this change.quoted
&enet0 { status = "okay"; };diff --git a/arch/mips/boot/dts/brcm/bcm97360svmb.dts b/arch/mips/boot/dts/brcm/bcm97360svmb.dts index 496e6ed9fae3..a445a45f51cb 100644 --- a/arch/mips/boot/dts/brcm/bcm97360svmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97360svmb.dts@@ -49,6 +49,14 @@ status = "okay";}; +&upg_gio { + status = "okay"; +}; + +&upg_gio_aon { + status = "okay"; +}; +You don't set their status in the dtsi, they will be enabled by default, and you can drop this change.quoted
&enet0 { status = "okay"; };diff --git a/arch/mips/boot/dts/brcm/bcm97362svmb.dts b/arch/mips/boot/dts/brcm/bcm97362svmb.dts index b880c018f3d8..22b1b506594f 100644 --- a/arch/mips/boot/dts/brcm/bcm97362svmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97362svmb.dts@@ -45,6 +45,14 @@ status = "okay";}; +&upg_gio { + status = "okay"; +}; + +&upg_gio_aon { + status = "okay"; +}; +You don't set their status in the dtsi, they will be enabled by default, and you can drop this change.quoted
&enet0 { status = "okay"; };diff --git a/arch/mips/boot/dts/brcm/bcm97420c.dts b/arch/mips/boot/dts/brcm/bcm97420c.dts index e66271af055e..428c36da91b6 100644 --- a/arch/mips/boot/dts/brcm/bcm97420c.dts +++ b/arch/mips/boot/dts/brcm/bcm97420c.dts@@ -59,6 +59,10 @@ status = "okay";}; +&upg_gio { + status = "okay"; +}; +You don't set its status in the dtsi, it will be enabled by default, and you can drop this change.quoted
/* FIXME: MAC driver comes up but cannot attach to PHY */ &enet0 { status = "disabled";diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts index f091e91b11c5..6adfcd505a03 100644 --- a/arch/mips/boot/dts/brcm/bcm97425svmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts@@ -59,6 +59,14 @@ status = "okay";}; +&upg_gio { + status = "okay"; +}; + +&upg_gio_aon { + status = "okay"; +}; +You don't set their status in the dtsi, they will be enabled by default, and you can drop this change.quoted
&enet0 { status = "okay"; };diff --git a/arch/mips/boot/dts/brcm/bcm97435svmb.dts b/arch/mips/boot/dts/brcm/bcm97435svmb.dts index 9db84f2a6664..dd8b8fb97053 100644 --- a/arch/mips/boot/dts/brcm/bcm97435svmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97435svmb.dts@@ -59,6 +59,14 @@ status = "okay";}; +&upg_gio { + status = "okay"; +}; + +&upg_gio_aon { + status = "okay"; +}; +You don't set their status in the dtsi, they will be enabled by default, and you can drop this change.quoted
&enet0 { status = "okay"; };Regards Jonas
The status="disabled" has been missing. It will be added in v2.
The interrupt-controller@ will also be changed.
Thanks,
Jaedon
From jaedon.shin@gmail.com Tue Aug 9 03:52:41 2016
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Subject: Re: [PATCH 4/4] MIPS: BMIPS: Add support NAND device nodes
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Date: Tue, 9 Aug 2016 10:52:30 +0900
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Hi Florian,
On Aug 9, 2016, at 7:40 AM, Florian Fainelli [off-list ref] wrote:On 08/08/2016 03:35 PM, Florian Fainelli wrote:quoted
On 08/07/2016 07:17 PM, Jaedon Shin wrote:quoted
Adds NAND device nodes to BCM7xxx MIPS based SoCs. Signed-off-by: Jaedon Shin <redacted> --- arch/mips/boot/dts/brcm/bcm7125.dtsi | 20 ++++++++++++++++++ arch/mips/boot/dts/brcm/bcm7346.dtsi | 20 ++++++++++++++++++ arch/mips/boot/dts/brcm/bcm7358.dtsi | 20 ++++++++++++++++++ arch/mips/boot/dts/brcm/bcm7360.dtsi | 20 ++++++++++++++++++ arch/mips/boot/dts/brcm/bcm7362.dtsi | 20 ++++++++++++++++++ arch/mips/boot/dts/brcm/bcm7420.dtsi | 20 ++++++++++++++++++ arch/mips/boot/dts/brcm/bcm7425.dtsi | 20 ++++++++++++++++++ arch/mips/boot/dts/brcm/bcm7435.dtsi | 20 ++++++++++++++++++ arch/mips/boot/dts/brcm/bcm7xxx-nand-cs1-bch8.dtsi | 24 ++++++++++++++++++++++ arch/mips/boot/dts/brcm/bcm97125cbmb.dts | 5 +++++ arch/mips/boot/dts/brcm/bcm97346dbsmb.dts | 5 +++++ arch/mips/boot/dts/brcm/bcm97358svmb.dts | 5 +++++ arch/mips/boot/dts/brcm/bcm97360svmb.dts | 5 +++++ arch/mips/boot/dts/brcm/bcm97362svmb.dts | 5 +++++ arch/mips/boot/dts/brcm/bcm97420c.dts | 5 +++++ arch/mips/boot/dts/brcm/bcm97425svmb.dts | 5 +++++ arch/mips/boot/dts/brcm/bcm97435svmb.dts | 5 +++++ 17 files changed, 224 insertions(+) create mode 100644 arch/mips/boot/dts/brcm/bcm7xxx-nand-cs1-bch8.dtsidiff --git a/arch/mips/boot/dts/brcm/bcm7125.dtsi b/arch/mips/boot/dts/brcm/bcm7125.dtsi index 746ed06c85de..8642631a8451 100644 --- a/arch/mips/boot/dts/brcm/bcm7125.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7125.dtsi@@ -226,5 +226,25 @@interrupts = <61>; status = "disabled"; }; + + hif_l2_intc: hif_l2_intc@411000 { + compatible = "brcm,l2-intc"; + reg = <0x411000 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <0>; + }; + + nand: nand@412800 { + compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "nand"; + reg = <0x412800 0x400>; + interrupt-parent = <&hif_l2_intc>; + interrupts = <24>; + status = "disabled"; + };This is a NAND v3.3 controller here not a v5.0 and it uses the EDU registers for DMA transfers which is not supported in the mainline driver, so with that dropped, the series looks fine. At any rate this would require additional brcmnand changes to be supported.The same applies to the 7420 DTS, it's also a v3.3 NAND controller -- Florian
The NAND device nodes of v3.3 NAND controller will be removed in v2.
Thanks,
Jaedon
From keguang.zhang@gmail.com Tue Aug 9 10:22:50 2016
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From: Keguang Zhang <keguang.zhang@gmail.com>
To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Cc: Ralf Baechle <redacted>,
Kelvin Cheung [off-list ref]
Subject: [PATCH V1] MIPS: Loongson1B: Provide DMA filter callbacks via platform data
Date: Tue, 9 Aug 2016 16:22:25 +0800
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From: Kelvin Cheung <keguang.zhang@gmail.com>
This patch provides DMA filter callbacks via platform data
to make NAND driver independent of single DMA engine driver.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
---
v1:
Fix the build error
---
arch/mips/include/asm/mach-loongson32/dma.h | 4 ++++
arch/mips/include/asm/mach-loongson32/nand.h | 3 +--
arch/mips/loongson32/ls1b/board.c | 3 +++
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson32/dma.h b/arch/mips/include/asm/mach-loongson32/dma.h
index ad1dec7..d3ae391 100644
--- a/arch/mips/include/asm/mach-loongson32/dma.h
+++ b/arch/mips/include/asm/mach-loongson32/dma.h@@ -12,6 +12,8 @@ #ifndef __ASM_MACH_LOONGSON32_DMA_H #define __ASM_MACH_LOONGSON32_DMA_H +#include <linux/dmaengine.h> + #define LS1X_DMA_CHANNEL0 0 #define LS1X_DMA_CHANNEL1 1 #define LS1X_DMA_CHANNEL2 2
@@ -22,4 +24,6 @@ struct plat_ls1x_dma { extern struct plat_ls1x_dma ls1b_dma_pdata; +bool ls1x_dma_filter(struct dma_chan *chan, void *param); + #endif /* __ASM_MACH_LOONGSON32_DMA_H */
diff --git a/arch/mips/include/asm/mach-loongson32/nand.h b/arch/mips/include/asm/mach-loongson32/nand.h
index e274912..a1f8704 100644
--- a/arch/mips/include/asm/mach-loongson32/nand.h
+++ b/arch/mips/include/asm/mach-loongson32/nand.h@@ -21,10 +21,9 @@ struct plat_ls1x_nand { int hold_cycle; int wait_cycle; + bool (*dma_filter)(struct dma_chan *chan, void *param); }; extern struct plat_ls1x_nand ls1b_nand_pdata; -bool ls1x_dma_filter_fn(struct dma_chan *chan, void *param); - #endif /* __ASM_MACH_LOONGSON32_NAND_H */
diff --git a/arch/mips/loongson32/ls1b/board.c b/arch/mips/loongson32/ls1b/board.c
index 38a1d40..dac1cbb 100644
--- a/arch/mips/loongson32/ls1b/board.c
+++ b/arch/mips/loongson32/ls1b/board.c@@ -38,6 +38,9 @@ struct plat_ls1x_nand ls1x_nand_pdata = { .nr_parts = ARRAY_SIZE(ls1x_nand_parts), .hold_cycle = 0x2, .wait_cycle = 0xc, +#ifdef CONFIG_LOONGSON1_DMA + .dma_filter = ls1x_dma_filter, +#endif }; static const struct gpio_led ls1x_gpio_leds[] __initconst = {
--
1.9.1