Thread (19 messages) 19 messages, 4 authors, 2016-01-28

Re: [PATCH 5/6] MIPS: Loongson: Introduce and use cpu_has_coherent_cache feature

From: James Hogan <hidden>
Date: 2016-01-27 11:16:05

Hi Huacai,

On Wed, Jan 27, 2016 at 12:58:42PM +0800, Huacai Chen wrote:
"cache coherency" here means the coherency across cores, not ic/dc
coherency, could you please suggest a suitable name?
Data cache coherency across cores is pretty much a requirement for SMP.
It looks more like for various reasons you can skip the cache management
functions, e.g.
quoted
quoted
@@ -503,6 +509,9 @@ static void r4k_flush_cache_range(struct vm_area_struct *vma,
 {
      int exec = vma->vm_flags & VM_EXEC;

+     if (cpu_has_coherent_cache)
+             return;
This seems to suggest:
1) Your dcaches don't alias.
2) Your icache is coherent with your dcache, otherwise you would need to
   flush the icache here so that mprotect RW->RX makes code executable
   without risk of stale lines existing in icache.

So, is that the case?

If so, it would seem better to ensure that cpu_has_dc_aliases evaluates
to false, and add a similar one for icache coherency, hence my original
suggestion.

quoted
quoted
+
      if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
              r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
(Note, this cpu_has_ic_fills_f_dc check is wrong, it shouldn't prevent
icache flush, see http://patchwork.linux-mips.org/patch/12179/)

Cheers
James
quoted
quoted
 }
@@ -627,6 +636,9 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma,
 {
      struct flush_cache_page_args args;

+     if (cpu_has_coherent_cache)
+             return;
+
      args.vma = vma;
      args.addr = addr;
      args.pfn = pfn;
@@ -636,11 +648,17 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma,

 static inline void local_r4k_flush_data_cache_page(void * addr)
 {
+     if (cpu_has_coherent_cache)
+             return;
+
      r4k_blast_dcache_page((unsigned long) addr);
 }

 static void r4k_flush_data_cache_page(unsigned long addr)
 {
+     if (cpu_has_coherent_cache)
+             return;
+
      if (in_atomic())
              local_r4k_flush_data_cache_page((void *)addr);
      else
@@ -825,6 +843,9 @@ static void local_r4k_flush_cache_sigtramp(void * arg)

 static void r4k_flush_cache_sigtramp(unsigned long addr)
 {
+     if (cpu_has_coherent_cache)
+             return;
+
      r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
 }

--
2.4.6



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