This series introduces support for the Memory Accessibility Attribute
Registers introduced with MIPSr5. These registers control whether
speculative accesses are allowed to regions of memory. Allowing
speculative memory accesses is a requirement for current hardware MSA
implementations to be able to handle non-128b aligned vector loads &
stores, which are something userland may legitimately assume will work.

The series needs Markos' "MIPS: cpu-info: Change the cpu options
variable to unsigned long long" patch to be applied first.

Paul Burton (4):
  MIPS: define MAAR register accessors & bits
  MIPS: detect presence of MAARs
  MIPS: initialise MAARs
  MIPS: Malta: initialise MAARs

 arch/mips/include/asm/cpu-features.h |   3 +
 arch/mips/include/asm/cpu.h          |   1 +
 arch/mips/include/asm/maar.h         | 109 +++++++++++++++++++++++++++++++++++
 arch/mips/include/asm/mipsregs.h     |  12 ++++
 arch/mips/kernel/cpu-probe.c         |   2 +
 arch/mips/mm/init.c                  |  33 +++++++++++
 arch/mips/mti-malta/malta-memory.c   |  26 +++++++++
 7 files changed, 186 insertions(+)
 create mode 100644 arch/mips/include/asm/maar.h

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2.0.1