Re: [PATCH 2/2] SPI: ralink: add Ralink SoC spi driver

On Tue, Aug 13, 2013 at 08:43:51PM +0200, John Crispin wrote:

quoted

There is presumably a maximum transfer size here from the FIFO that is
holding the data?

The hardware is not running in DMA/IRQ mode and hence it can only
read/write 1 byte at a time.

OK, then the code looks buggy since it does all the Tx then all the Rx
so a bidirectional transfer should fail.  I'd expect Tx and Rx to be
part of the same loop in this case.

quoted

Set min_speed_hz in the spi_master and the core will check this for you.

it seems that min_speed is not handled by the core yet. I saw
several drivers do minimum speed testing. I am leaving this code in
the driver until there is a generic minimum speed check

Or add the check to the core...

quoted

clk_prepare_enable(), and it'd be nice to use runtime PM and enable the
clock only when doing transfers though that's not essential.

The clock is free running and always running.

It's still nice to turn it off for power, and very cheap to implement.