Hi, Steven

Is the 3rd patch of V10 is OK to be accepted now? If so, could the
patchset of V10 be merged into 3.11?

Huacai

On Fri, Apr 12, 2013 at 11:07 AM, Huacai Chen [off-list ref] wrote:

Hi, Steven,

Maybe you are misunderstand Loongson-3's "hardware-maintained cache".
Loongson-3's hardware maintain the cache coherency between multi-cores (also
maintain coherency between CPU-core and DMA), but Loongson-3 can *still* has
cache alias (Cache alias in Loongson is sovled by 16K PageSize).

Meanwhile, I know why you misunderstand, because my code is like this:


static inline void local_r4k___flush_cache_all(void * args)
        if (cpu_has_coherent_cache)
                return;

This implies that Loongson-3 has no cache alias, but in fact this is wrong
if Loongson has configured PageSize < 16K.

I think I should make my code in all flush functions like this:

static inline void local_r4k___flush_cache_all(void * args)
        if (cpu_has_coherent_cache && !cpu_has_dc_aliases)
                return;

Am I right?


On Fri, Apr 12, 2013 at 1:05 AM, Steven J. Hill [off-list ref]
wrote:

quoted

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Hash: SHA1

On 01/30/2013 12:24 AM, Huacai Chen wrote:

quoted

Loongson-3 maintains cache coherency by hardware. So we introduce a cpu
feature named cpu_has_coherent_cache and use it to modify MIPS's cache
flushing functions.

Signed-off-by: Huacai Chen <redacted> Signed-off-by: Hongliang
Tao
[off-list ref] Signed-off-by: Hua Yan [off-list ref] ---
arch/mips/include/asm/cacheflush.h                 |    6 +++++
arch/mips/include/asm/cpu-features.h               |    3 ++
.../asm/mach-loongson/cpu-feature-overrides.h      |    6 +++++
arch/mips/mm/c-r4k.c                               |   21
++++++++++++++++++- 4 files changed, 34 insertions(+), 2 deletions(-)

Hello.

This patch masks the problem that you are not properly probing your L1
caches
to start with. For some reason in 'probe_pcache()' you reach the default
case
where the primary data cache is marked as having aliases. If your CPU
truly is
HW coherent with no aliases, then MIPS_CACHE_ALIASES should never get set.
Fixing this would eliminate the 'arch/mips/include/asm/cacheflush.h' and
'arch/mips/mm/c-r4k.c' changes completely. There is no need to add more
CPU
feature bits for this single platform, thus changes to 'cpu-features.h'
and
'cpu-features-overrides.h' will not be accepted.

Also, please do not copy the [off-list ref] mailing list
unless your patch touches files outside of 'arch/mips' in order to cut
down
traffic on an already busy list. Thanks.

Steve
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[off-list ref]
[off-list ref]
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