Re: [PATCH 2/5] MIPS: Clean-up GIC and vectored interrupts.
From: Ralf Baechle <hidden>
Date: 2012-05-30 08:49:00
On Fri, Apr 06, 2012 at 12:59:00PM -0500, Steven J. Hill wrote:
From: "Steven J. Hill" <redacted> This change adds macros for routing of GIC interrupts for EIC and non-EIC hardware modes. Also added Malta GIC macros having to do with performance and timer interrupts. Signed-off-by: Steven J. Hill <redacted>
quoted hunk ↗ jump to hunk
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index fb698dc..78dbb8a 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h@@ -136,6 +136,7 @@ extern void free_irqno(unsigned int irq); * IE7. Since R2 their number has to be read from the c0_intctl register. */ #define CP0_LEGACY_COMPARE_IRQ 7 +#define CP0_LEGACY_PERFCNT_IRQ 7 extern int cp0_compare_irq; extern int cp0_compare_irq_shift;
I split of this segment into a separate commit because it appeared to be unrelated to the rest of the patch and also made use of the symbol in traps.c. Thanks, Ralf